Dynamic wordline start voltage for nand programming
View Patent ↗The present invention discloses a method of programming an MLC NAND flash memory device comprising: selecting a start value for a program voltage for a lower page; incrementing said program voltage to program said lower page; verifying a threshold voltage; determining said program voltage to achieve a desired value for said threshold voltage; applying an offset to said program voltage; and obtaining a start value for said program voltage for an upper page.
1. A method of programming an MLC NAND flash memory device comprising:
selecting a start value for a program voltage for a lower page;
incrementing said program voltage to program said lower page, wherein an incremental change amount for the program voltage varies between an odd page and an even page;
verifying a threshold voltage;
determining said program voltage to achieve a desired value for said threshold voltage;
applying an offset to said program voltage; and
obtaining a start value for said program voltage for an upper page.
2. The method of claim 1 wherein programming said lower page of said MLC NAND is similar to programming an SLC NAND flash memory device.
3. The method of claim 1 wherein said lower page comprises one erased state and one programmed state.
4. The method of claim 1 wherein said lower page comprises a state of “1” for said erased state.
5. The method of claim 1 wherein said lower page comprises a state of “0” for said programmed state.
6. The method of claim 1 wherein said upper page comprises one erased state and three programmed states.
7. The method of claim 1 wherein said upper page comprises a state of “11” for said erased state.
8. The method of claim 1 wherein said upper page comprises three programmed states of “01”, “00”, and “10”.
9. An MLC NAND flash memory device comprising:
incrementing a first program voltage to program said lower page, wherein an incremental change amount for the program voltage varies between an odd page and an even page;
a first program voltage to achieve a desired threshold voltage for a lower page; and
a second program voltage to achieve a desired threshold voltage for an upper page wherein an offset separates said first program voltage from said second program voltage.
10. The MLC NAND flash memory device of claim 9 wherein said lower page corresponds to a first bit.
11. The MLC NAND flash memory device of claim 9 wherein said upper page corresponds to a second bit.
12. The MLC NAND flash memory device of claim 9 wherein said lower page comprises a state of “1” for an erased state.
13. The MLC NAND flash memory device of claim 9 wherein said lower page comprises a state of “0” for a programmed state.
14. The MLC NAND flash memory device of claim 9 wherein said upper page comprises a state of “11” for an erased state.
15. The MLC NAND flash memory device of claim 9 wherein said upper page comprises three programmed states of “01”, “00”, and “10”.
16. A method of reducing programming time for an MLC NAND flash memory device comprising:
incrementing said program voltage to program said lower page, wherein an incremental change amount for the program voltage varies between an odd page and an even page;
determining a first program voltage to achieve a desired threshold voltage for a lower page;
applying an offset to said program voltage; and
obtaining a second program voltage to achieve a desired threshold voltage for an upper page.
17. The method of claim 16 wherein said lower page comprises a state of “1” for an erased state.
18. The method of claim 16 wherein said lower page comprises a state of “0” for a programmed state.
19. The method of claim 16 wherein said upper page comprises a state of “11” for an erased state.
20. The method of claim 16 wherein said upper page comprises three programmed states of “01”, “00”, and “10”.