Method and system for compensating for floating gate-to-floating gate (fg-fg) interference in flash memory cell read operations
View Patent ↗Embodiments of the present disclosure provide methods, devices, modules, and systems for compensating for floating gate to floating gate (fg-fg) interference in flash memory cell read operations. Compensating for fg-fg interference effects can reduce or prevent read errors. Embodiments of the present disclosure can compensate for fg-fg interference by determining the programmed state of aggressor (or influencing) memory cells that are programmed after a target memory cell. If the aggressor memory cell is in the erased state of Level 0 or is in a programmed state of Level 2 - 15 , the target memory cell is identified as undisturbed. If the aggressor memory cell is programmed to a Level 1 (instead of Level 0 or Levels 2 - 15 ), the target memory cell is identified as disturbed. If the target memory cell is disturbed, sensing parameters may be adjusted to compensate for the disruption.
1. A memory controller, comprising:
memory controller logic to:
receive a request to read data stored in a first memory cell of a multi-level non-volatile memory array, wherein the data includes at least 4 bits, wherein the first memory cell is in a first wordline;
perform a read operation on a second memory cell of the multi-level non-volatile memory array to determine if the second memory cell is programmed to a first programming level that is between an erased programming level and at least 14 other programming levels, the second memory cell being adjacent to the first memory cell on a memory cell string, wherein the second memory cell is operated with a second wordline that is adjacent to the first wordline, in response to the request;
assign a disturbed condition to the first memory cell responsive to a determination that the second memory cell is at the first programming level; and
read the data stored in the first memory cell, in response to the request, with a compensated sensing parameter responsive to the assignment of the disturbed condition to the first memory cell; and
error-correcting code logic to determine that the first memory cell is in the disturbed condition when the second memory cell is programmed to the first programming level.
2. The memory controller of claim 1 , wherein the first memory cell is read at a first threshold voltage in the disturbed condition and is read at a second threshold voltage in an undisturbed condition, wherein the first threshold voltage is higher than the second threshold voltage.
3. The memory controller of claim 1 , wherein the first memory cell and the second memory cell are two of a plurality of memory cells, wherein a threshold voltage distribution of an erased TLC programming level of the plurality of memory cells is at least 2-3 times wider than threshold voltage distributions of each of the 14 other programming levels.
4. The memory controller of claim 1 , wherein the first programming level is adjacent to the erased programming level, wherein the first programming level is a QLC Level 1 programming level, wherein the erased programming level is a QLC Level 0 programming level.
5. The memory controller of claim 1 , wherein the second memory cell is programmed to one of 8 TLC programming levels prior to the first memory cell being programmed to one of 16 QLC programming levels, wherein the first memory cell is programmed to one of 16 QLC programming levels prior to the second memory cell being programmed to one of 16 QLC programming levels.
6. The memory controller of claim 1 , wherein the first memory cell and the second memory cell are two of a plurality of memory cells, wherein the plurality of memory cells is programmed to one of 8 TLC programming levels in a first programming pass, prior to being programmed to one of 16 QLC programming levels in a second programming pass.
7. The memory controller of claim 1 , wherein the compensated sensing parameter includes an increased wordline read voltage level, an adjusted sense current, or an adjusted bitline voltage level, to compensate for an increased threshold voltage from the disturbed condition of the first memory cell.
8. A system, comprising:
a display;
a memory array having a plurality of memory cells; and
a memory controller, comprising:
memory controller logic to:
receive a request to read data stored in a first memory cell of a non-volatile memory array, wherein the data includes at least 4 bits, wherein the first memory cell is in a first wordline;
perform a read operation on a second memory cell of the non-volatile memory array to determine if the second memory cell is programmed to a first programming level that is between an erased programming level and at least 14 other programming levels, the second memory cell being adjacent to the first memory cell on a memory cell string, wherein the second memory cell is operated with a second wordline that is adjacent to the first wordline, in response to the request;
assign a disturbed condition to the first memory cell responsive to a determination that the second memory cell is at the first programming level; and
read the data stored in the first memory cell, in response to the request, with a compensated sensing parameter responsive to the association of the first memory cell with the disturbed condition; and
error-correcting code logic to determine that the first memory cell is in the disturbed condition when the second memory cell is programmed to the first programming level.
9. The system of claim 8 , wherein the first memory cell is read at a first threshold voltage in the disturbed condition and is read at a second threshold voltage in an undisturbed condition, wherein the first threshold voltage is higher than the second threshold voltage.
10. The system of claim 8 , wherein the first memory cell and the second memory cell are two of a plurality of memory cells, wherein a threshold voltage distribution of an erased TLC programming level of the plurality of memory cells is at least 2-3 times wider than threshold voltage distributions of the 14 other programming levels.
11. The system of claim 8 , wherein the first programming level is adjacent to the erased programming level, wherein the first programming level is a QLC Level 1 programming level, wherein the erased programming level is a QLC Level 0 programming level.
12. The system of claim 8 , wherein the second memory cell is programmed to one of 8 TLC programming levels prior to the first memory cell being programmed to one of 16 QLC programming levels, wherein the first memory cell is programmed to one of 16 QLC programming levels prior to the second memory cell being programmed to one of 16 QLC programming levels.
13. The system of claim 8 , wherein the first memory cell and the second memory cell are two of a plurality of memory cells, wherein the plurality of memory cells is programmed to one of 8 TLC programming levels in a first programming pass, prior to being programmed to one of 16 QLC programming levels in a second programming pass.
14. The system of claim 8 , wherein the compensated sensing parameter includes an increased wordline read voltage level, an adjusted sense current, or an adjusted bitline voltage level, to compensate for an increased threshold voltage from the disturbed condition of the first memory cell.
15. A method, comprising:
receiving a request to read data stored in a first memory cell of a non-volatile memory array, wherein the data includes at least 4 bits, wherein the first memory cell is in a first wordline;
performing a read operation on a second memory cell of the non-volatile memory array, the second memory cell being adjacent to the first memory cell on a memory cell string, wherein the second memory cell is in a second wordline that is adjacent to the first wordline, in response to the request;
determining whether the second memory cell is programmed to a first programming level that is between an erased programming level and at least 14 other programming levels;
assigning a disturbed condition to the first memory cell, responsive to a determination that the second memory cell is at the first programming level; and
reading the data stored in the first memory cell, in response to the request, with a compensated sensing parameter responsive to assignment of the disturbed condition to the first memory cell.
16. The method of claim 15 , wherein the first memory cell is read at a first threshold voltage in the disturbed condition and is read at a second threshold voltage in an undisturbed condition, wherein the first threshold voltage is higher than the second threshold voltage.
17. The method of claim 15 , wherein the first programming level is adjacent to the erased programming level, and the first programming level is a QLC Level 1 programming level, while the erased programming level is a QLC Level 0 programming level.
18. The method of claim 15 , wherein the first memory cell and the second memory cell are two of a plurality of memory cells, wherein the plurality of memory cells is programmed to one of 8 TLC programming levels in a first programming pass, prior to being programmed to one of 16 QLC programming levels in a second programming pass.
19. The method of claim 15 , wherein the compensated sensing parameter includes an increased wordline read voltage level, an adjusted sense current, or an adjusted bitline voltage level, to compensate for an increased threshold voltage from the disturbed condition of the first memory cell.