Sensing with boost
The present disclosure relates to sensing with boost. An apparatus includes boost logic. Boost logic includes a boost source and a plurality of boost interfaces coupled to the boost source. The boost source is configured to provide a boost clamp voltage to each of the plurality of boost interfaces. Each of the plurality of boost interfaces includes a respective buffer configured to buffer the boost source from a respective load. Each boost interface is configured to provide a boost voltage to the respective load. The boost voltage configured to increase a sense window. The boost voltage related to the boost clamp voltage.
1. An apparatus comprising:
boost logic comprising:
a boost source; and
a plurality of boost interfaces coupled to the boost source,
the boost source configured to provide a boost clamp voltage to each of the plurality of boost interfaces, each of the plurality of boost interfaces comprising a respective buffer configured to buffer the boost source from a respective load, each boost interface configured to provide a boost voltage to the respective load, the boost voltage configured to increase a sense window, the boost voltage related to the boost clamp voltage.
2. The apparatus of claim 1 , wherein the boost logic comprises boost reset logic configured to controllably reset the boost voltage.
3. The apparatus of claim 1 , wherein the boost logic further comprises boost discharge logic configured to reduce the boost voltage from a first boost voltage to a second boost voltage less than the first boost voltage.
4. The apparatus of claim 2 , wherein the boost interface comprises at least a portion of the boost reset logic, the portion comprising a transistor configured to controllably couple a boost local node to a ground.
5. The apparatus of claim 3 , wherein the boost source and the boost interface each comprise a respective portion of the boost discharge logic, the boost source portion comprising a current generator and the boost interface comprising a transistor configured to mirror current generator current in the boost interface, a discharge rate related to the mirrored current.
6. The apparatus of claim 3 , wherein the boost interface comprises at least a portion of the boost discharge logic, the portion comprising a boost discharge transistor coupled to an output of the buffer.
7. The apparatus of claim 3 , wherein the boost source comprises at least a portion of the boost discharge logic, the boost source portion comprising a regulator configured to control the second boost voltage.
8. The apparatus of claim 1 , wherein a number of boost interfaces is greater than ten thousand.
9. A method comprising:
providing, by a boost source, a boost clamp voltage to each of a plurality of boost interfaces;
buffering, by each boost interface, the boost source from a respective load;
providing, by each boost interface, a boost voltage to the respective load, the boost voltage configured to increase a sense window, the boost voltage related to the boost clamp voltage.
10. The method of claim 9 , further comprising:
controllably resetting, by boost reset logic, the boost voltage.
11. The method of claim 9 , further comprising:
reducing, by boost discharge logic, the boost voltage from a first boost voltage to a second boost voltage less than the first boost voltage.
12. The method of claim 10 , wherein the boost interface comprises at least a portion of the boost reset logic and further comprising controllably coupling, by a transistor included in the at least a portion of the boost reset logic, a boost local node to a ground.
13. The method of claim 11 , wherein the boost source and the boost interface each comprise a respective portion of the boost discharge logic, the boost source portion comprising a current generator and the boost interface comprising a transistor and further comprising, generating, by the current generator, a current, and mirroring, by the transistor, the generated current in the boost interface, a discharge rate related to the mirrored current.
14. The method of claim 11 , wherein the boost interface comprises at least a portion of the boost discharge logic, the portion comprising a boost discharge transistor coupled to an output of the buffer.
15. The method of claim 11 , wherein the boost source comprises at least a portion of the boost discharge logic, and further comprising, controlling, by a regulator included in the boost source portion, the second boost voltage.
16. A system comprising:
a processor;
a chipset configured to couple the processor to a peripheral device;
a memory array comprising a plurality of memory cells; and
a memory controller comprising:
boost logic comprising:
a boost source; and
a plurality of boost interfaces coupled to the boost source,
the boost source configured to provide a boost clamp voltage to each of the plurality of boost interfaces, each of the plurality of boost interfaces comprising a respective buffer configured to buffer the boost source from a respective load, each boost interface configured to provide a boost voltage to the respective load, the boost voltage configured to increase a sense window, the boost voltage related to the boost clamp voltage.
17. The system of claim 16 , wherein the boost logic comprises boost reset logic configured to controllably reset the boost voltage.
18. The system of claim 16 , wherein the boost logic further comprises boost discharge logic configured to reduce the boost voltage from a first boost voltage to a second boost voltage less than the first boost voltage.
19. The system of claim 17 , wherein the boost interface comprises at least a portion of the boost reset logic, the portion comprising a transistor configured to controllably couple a boost local node to a ground.
20. The system of claim 18 , wherein the boost source and the boost interface each comprise a respective portion of the boost discharge logic, the boost source portion comprising a current generator and the boost interface comprising a transistor configured to mirror current generator current in the boost interface, a discharge rate related to the mirrored current.
21. The system of claim 18 , wherein the boost interface comprises at least a portion of the boost discharge logic, the portion comprising a boost discharge transistor coupled to an output of the buffer.
22. The system of claim 18 , wherein the boost source comprises at least a portion of the boost discharge logic, the boost source portion comprising a regulator configured to control the second boost voltage.
23. The system of claim 16 , wherein the memory comprises NAND flash memory.
24. The system of claim 16 , wherein each of the plurality of boost interfaces is included in a respective sense amplifier.
25. The system of claim 16 , wherein each load comprises a respective sense capacitor controllably coupled to a respective string of memory cells.