NAND memory devices systems, and methods using pre-read error recovery protocols of upper and lower pages

1. A NAND memory device, comprising:

an array of NAND memory cells; and

a controller configured to:

apply initial programming pulses for lower page programming of a page;

pre-read data of a lower page;

determine whether to apply an error recovery operation to the data of the lower page;

store data indicative of secondary programming pulses to be used for programming upper page data; and

program the upper page data based on the secondary programming pulses and the data of the lower page; wherein when programming lower sub-blocks of the upper page a first error recovery operation is applied, when programming middle sub-blocks of the upper page a second error recovery operation is applied, and when programming higher sub-blocks of the upper page a third error recovery operation is applied and wherein either:

each of the first, second and third error recovery operations are different; or

the lower sub-blocks, middle sub-blocks, and higher sub-blocks are groups of sub-blocks each comprising an equal number of sub-blocks; or

the lower sub-blocks, middle sub-blocks, and higher sub-blocks are groups of sub-blocks each comprising an equal number of sub-blocks; or

each of the first, second and third error recovery operations have different time costs.

2. The memory device of claim 1 , wherein determining whether to apply the error recovery operation to the data of the lower page comprises determining whether programming the upper page data comprises programming a lower sub-block or programming a higher sub-block, the method further comprising forgoing error recovery for the lower sub-block and applying the error recovery for the higher sub-block.

3. The memory device of claim 1 , wherein determining whether to apply the error recovery operation to the data of the lower page comprises determining a number of programming cycles for the lower page and applying the error recovery operation when the number of programming cycles exceeds a predetermined threshold.

4. The memory device of claim 1 , wherein the error recovery operation comprises a plurality of different error recovery operations that vary based on a word line location for the upper page programming.

5. The memory device of claim 1 , wherein the error recovery operation comprises a plurality of different error recovery operations that vary based on a combination of word line location for upper page programming, sub-block for the upper page programming or cycle count for the pre-reading of the data of the lower page.

6. The memory device of claim 1 , further comprising progressively applying increasingly time costly error recovery to the data of the lower page when programming sub-blocks of the upper page.

7. A data storage system, comprising:

a processor;

a power source; and

a NAND memory as recited in claim 1 coupled to the processor.

8. The system of claim 7 , wherein the error recovery operation comprises a plurality of different error recovery operations that vary based on a word line location for the upper page programming.

9. The system of claim 7 , wherein the error recovery comprises interference compensation by modifying a read voltage of a sub-block of the data of the lower page based on a read voltage of an adjacent wordline.

10. The system of claim 9 , wherein the read voltage of the sub-block of the data of the lower page is modified based on the read voltage of a single adjacent wordline.

11. The system of claim 9 , wherein the read voltage of the sub-block of the data of the lower page is modified based on the read voltage of multiple adjacent wordlines.

12. The system of claim 7 , wherein the error recovery operation comprises outputting the pre-read data of the lower page to the controller, correcting the lower page data with the controller, and using the corrected data for programming the upper page data.

13. The system of claim 7 , wherein the error recovery operation comprises a read voltage search, using the controller that determines a read voltage for a minimum bit error rate and adjusts a read voltage of the data of the lower page based on the read voltage for the minimum bit error rate.

14. A computer-implemented method of programming a page of a memory in a NAND memory device, comprising:

applying initial programming pulses for lower page programming of a page;

pre-reading data of a lower page;

determining whether to apply an error recovery operation to the data of the lower page;

storing data indicative of secondary programming pulses to be used for programming upper page data;

programming the upper page data based on the secondary programming pulses and the data of the lower page; and further comprising:

storing data indicative of tertiary programming pulses to be used for programming middle page data;

programming the middle page data based on the tertiary programming pulses and the data of the lower page; and

pre-reading the middle page data;

wherein programming the upper page data based on the secondary programming pulses and the data of the lower page comprises programming the upper page data based on the secondary pulses and the data of the middle page, the middle page data being programmed based on the data of the lower page.