IP Library Granted Patent US 8,943,385
Granted Patent B2
US 8,943,385 · App. 13/658,449 · Granted Jan 27, 2015

NAND memory management

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,943,385
App. No.
13/658,449
Granted
Jan 27, 2015
Kind
B2
Abstract

Apparatus, systems, and methods to manage NAND memory are described. In one embodiment, a memory controller logic is configured to apply a binary parity check code to a binary string and convert the binary string to a ternary string.

Claims (47)

1. An apparatus comprising:

a memory controller logic to:

apply a binary parity check code to a binary string; and

convert the binary string to a ternary string

determine, for each ternary combination in a set of 2187 ternary combinations, a number of neighbors which have a hamming distance of 1 from the ternary combination;

order the set of 2187 ternary combinations in ascending order of the number of neighbors which having a hamming distance of 1;

remove from the set of 2187 ternary combinations a subset of 139 ternary combinations to produce a set of 2048 ternary combinations;

select as a root a ternary combination which has 11 neighbors;

assign vertices for all ternary combinations which have a hamming distance of 1 from the root;

iteratively populate the mapping tree with nodes having a hamming distance of 1 from their respective neighbors.

2. The apparatus of claim 1 , further comprising logic to write the ternary string to a 3-level NAND memory.

3. The apparatus of claim 1 , further comprising logic to:

assign a binary 0 string to the root node;

assign binary strings which have a single 1 to the 11 neighbors of the root node; and

iteratively assign binary strings which have a hamming distance of 1 to the vertices of each node in the mapping tree.

4. The apparatus of claim 1 wherein one or more processor cores are coupled to the memory controller logic to access data stored in the 3-level NAND memory.

5. A system comprising:

a 3-level NAND memory device having a plurality of memory cells;

a processor to access the 3-level NAND memory device; and

a 3-level NAND memory controller logic to:

apply a binary parity check code to a binary string; and

convert the binary string to a ternary string

determine, for each ternary combination in a set of 2187 ternary combinations, a number of neighbors which have a hamming distance of 1 from the ternary combination;

order the set of 2187 ternary combinations in ascending order of the number of neighbors which having a hamming distance of 1;

remove from the set of 2187 ternary combinations a subset of 139 ternary combinations to produce a set of 2048 ternary combinations;

select as a root a ternary combination which has 11 neighbors;

assign vertices for all ternary combinations which have a hamming distance of 1 from the root;

iteratively populate the mapping tree with nodes having a hamming distance of 1 from their respective neighbors.

6. The system of claim 5 , further comprising logic to write the ternary string to the 3-level NAND memory.

7. The system of claim 5 , further comprising logic to:

assign a binary 0 string to the root node;

assign binary strings which have a single 1 to the 11 neighbors of the root node; and

iteratively assigning binary strings which have a hamming distance of 1 to the vertices of each node in the mapping tree.

8. A computer-implemented method comprising:

applying a binary parity check code to a binary string; and

converting the binary string to a ternary string

determining, for each ternary combination in a set of 2187 ternary combinations, a number of neighbors which have a hamming distance of 1 from the ternary combination;

ordering the set of 2187 ternary combinations in ascending order of the number of neighbors which having a hamming distance of 1;

removing from the set of 2187 ternary combinations a subset of 139 ternary combinations to produce a set of 2048 ternary combinations;

selecting as a root a ternary combination which has 11 neighbors;

assigning vertices for all ternary combinations which have a hamming distance of 1 from the root

Iteratively populating the mapping tree with nodes having a hamming distance of 1 from their respective neighbors; and

writing the ternary string to a 3-level NAND memory.

9. The method of claim 8 , further comprising:

assigning a binary 0 string to the root node;

assigning binary strings which have a single 1 to the 11 neighbors of the root node; and

iteratively assigning binary strings which have a hamming distance of 1 to the vertices of each node in the mapping tree.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2023
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 064928/0832 →