Memory block access modes for a storage device
Technology for a NAND memory is described. The NAND memory can include a first-type dedicated memory block. The NAND memory can include a second-type dedicated memory block. The NAND memory can include logic to perform a data operation on the first-type dedicated memory block using a first first-type access mode. The NAND memory can include logic to perform a data operation on the variable-type memory block using a second first-type access mode.
1. A NAND memory, comprising:
a variable-type memory block;
a first-type dedicated memory block;
a second-type dedicated memory block; and
logic configured to:
perform a data operation on the first-type dedicated memory block using a first first-type access mode; and
perform a data operation on the variable-type memory block using a second first-type access mode.
2. The NAND memory of claim 1 , wherein the first first-type access mode is a first single-level cell (SLC) on-the-fly (OTF) user access mode and the second first-type access mode is a second SLC OTF user access mode.
3. The NAND memory of claim 1 , wherein the first first-type access mode is associated with a first trim set and the second first-type access mode is associated with a second trim set that is different than the first trim set.
4. The NAND memory of claim 1 , wherein the second first-type access mode preserves a cycling endurance and a raw bit error rate (RBER) for the variable-type memory block.
5. The NAND memory of claim 1 , wherein the second first-type access mode is selectable via a memory command.
6. The NAND memory of claim 1 , wherein the second first-type access mode is selectable via a set feature command.
7. The NAND memory of claim 1 , wherein the logic is further configured to perform a data operation on the second-type dedicated memory block using a second-type access mode, wherein the second-type access mode is a triple-level cell (TLC) or quad-level cell (QLC) user access mode.
8. The NAND memory of claim 1 , wherein the logic is further configured to perform a data operation on the variable-type memory block using a second-type access mode, wherein the second-type access mode is a triple-level cell (TLC) or quad-level cell (QLC) user access mode.
9. The NAND memory of claim 1 , wherein the variable-type memory block is a single-level cell (SLC) memory block or a triple/quad-level cell (TLC/QLC) memory block on a per cycle basis.
10. The NAND memory of claim 1 , wherein the first-type dedicated memory block is a single-level cell (SLC) dedicated memory block.
11. The NAND memory of claim 1 , wherein the second-type dedicated memory block is a triple-level cell (TLC) dedicated memory block or a quad-level cell (QLC) dedicated memory block.
12. The NAND memory of claim 1 , wherein the logic is further configured to:
initialize defined variable-type memory blocks in the NAND memory to be accessible via the second first-type access mode; and
initialize defined first-type dedicated memory blocks in the NAND memory to be accessible via the first first-type access mode.
13. The NAND memory of claim 1 , wherein the data operation is one of: a read operation, a write operation or an erase operation.
14. A method for performing data operations on a NAND memory, the method comprising:
performing a data operation on a first-type dedicated memory block in the NAND memory using a first first-type access mode; and
performing a data operation on a variable-type memory block in the NAND memory using a second first-type access mode.
15. The method of claim 14 , further comprising performing a data operation on a second-type dedicated memory block in the NAND memory using a second-type access mode, wherein the second-type access mode is a triple-level cell (TLC) or quad-level cell (QLC) user access mode.
16. The method of claim 14 , further comprising performing a data operation on the variable-type memory block in the NAND memory using a second-type access mode, wherein the second-type access mode is a triple-level cell (TLC) or quad-level cell (QLC) user access mode.
17. The method of claim 14 , further comprising:
initializing defined variable-type memory blocks in the NAND memory to be accessible via the second first-type access mode; and
initializing defined first-type dedicated memory blocks in the NAND memory to be accessible via the first first-type access mode.
18. The method of claim 14 , wherein the first first-type access mode is a first single-level cell (SLC) on-the-fly (OTF) user access mode and the second first-type access mode is a second SLC OTF user access mode.
19. The method of claim 14 , wherein:
the second first-type access mode is selectable via a memory command; or
the second first-type access mode is selectable via a set feature command.
20. The method of claim 14 , wherein:
the variable-type memory block is a single-level cell (SLC) memory block or a triple/quad-level cell (TLC/QLC) memory block on a per cycle basis;
first-type dedicated memory block is a SLC dedicated memory block; and
the second-type dedicated memory block is a TLC dedicated memory block or a QLC dedicated memory block.