Dynamic single level cell memory controller
An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.
1. An electronic apparatus, comprising:
one or more substrates; and
logic coupled to the one or more substrates, the logic to:
control access to a memory array which includes a single-level cell region and a multi-level cell region,
determine a total amount of valid data in a dynamic portion of the single-level cell region at runtime,
adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined total amount of valid data in the dynamic portion of the single-level cell region,
increase the size of the dynamic portion in a first mode,
maintain the size of the dynamic portion in a second mode,
decrease the size of the dynamic portion in a third mode,
determine if a first condition is attained where a number of super blocks in the dynamic portion of the single-level cell region is equal to or greater than a first threshold,
determine if a second condition is attained where a total amount of mapped valid data in the dynamic portion of the single-level cell region is equal to or greater than a second threshold, and
determine if a third condition is attained where a number of empty blocks in the multi-level cell region is equal to or less than a third threshold.
2. The apparatus of claim 1 , wherein the logic is further to:
operate in the first mode when none of the first condition, the second condition, or the third condition is attained;
operate in the second mode when either the first condition or the second condition is attained and the third condition is not attained; and
operate in the third mode when the third condition is attained.
3. The apparatus of claim 2 , wherein the logic is further to:
write all host data to the dynamic portion of the single-level cell region in the first mode.
4. The apparatus of claim 2 , wherein the logic is further to:
write all host data to the dynamic portion of the single-level cell region in the second mode; and
perform a background move of copies of previously written data from the dynamic portion of the single-level cell region to the multi-level cell region in the second mode.
5. The apparatus of claim 2 , wherein the logic is further to:
write all host data to a static portion of the single-level cell region in the third mode; and
perform a background move of copies of previously written data from both the static and dynamic portions of the single-level cell region to the multi-level cell region in the third mode.
6. A storage system, comprising:
a memory array including a single-level cell region and a multi-level cell region; and
a controller coupled to the memory array, the controller including logic to:
determine a total amount of valid data in a dynamic portion of the single-level cell region at runtime,
adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined total amount of valid data in the dynamic portion of the single-level cell region,
increase the size of the dynamic portion in a first mode,
maintain the size of the dynamic portion in a second mode,
decrease the size of the dynamic portion in a third mode,
determine if a first condition is attained where a number of super blocks in the dynamic portion of the single-level cell region is equal to or greater than a first threshold,
determine if a second condition is attained where a total amount of mapped valid data in the dynamic portion of the single-level cell region is equal to or greater than a second threshold, and
determine if a third condition is attained where a number of empty blocks in the multi-level cell region is equal to or less than a third threshold.
7. The system of claim 6 , wherein the logic is further to:
operate in the first mode when none of the first condition, the second condition, or the third condition is attained;
operate in the second mode when either the first condition or the second condition is attained and the third condition is not attained; and
operate in the third mode when the third condition is attained.
8. The system of claim 7 , wherein the logic is further to:
write all host data to the dynamic portion of the single-level cell region in the first mode.
9. The system of claim 7 , wherein the logic is further to:
write all host data to the dynamic portion of the single-level cell region in the second mode; and
perform a background move of copies of previously written data from the dynamic portion of the single-level cell region to the multi-level cell region in the second mode.
10. The system of claim 7 , wherein the logic is further to:
write all host data to a static portion of the single-level cell region in the third mode; and
perform a background move of copies of previously written data from both the static and dynamic portions of the single-level cell region to the multi-level cell region in the third mode.
11. A method of controlling memory, comprising:
controlling access to a memory array which includes a single-level cell region and a multi-level cell region;
determining a total amount of valid data in a dynamic portion of the single-level cell region at runtime;
adjusting a size of the dynamic portion of the single-level cell region at runtime based on the determined total amount of valid data in the dynamic portion of the single-level cell region;
increasing the size of the dynamic portion in a first mode;
maintaining the size of the dynamic portion in a second mode;
decreasing the size of the dynamic portion in a third mode;
determining if a first condition is attained where a number of super blocks in the dynamic portion of the single-level cell region is equal to or greater than a first threshold;
determining if a second condition is attained where a total amount of mapped valid data in the dynamic portion of the single-level cell region is equal to or greater than a second threshold; and
determining if a third condition is attained where a number of empty blocks in the multi-level cell region is equal to or less than a third threshold.
12. The method of claim 11 , further comprising:
operating in the first mode when none of the first condition, the second condition, or the third condition is attained;
operating in the second mode when either the first condition or the second condition is attained and the third condition is not attained; and
operating in the third mode when the third condition is attained.
13. The method of claim 12 , further comprising:
writing all host data to the dynamic portion of the single-level cell region in the first mode.
14. The method of claim 12 , further comprising:
writing all host data to the dynamic portion of the single-level cell region in the second mode;
performing a background move of copies of previously written data from the dynamic portion of the single-level cell region to the multi-level cell region in the second mode;
writing all host data to a static portion of the single-level cell region in the third mode; and
performing a background move of copies of previously written data from both the static and dynamic portions of the single-level cell region to the multi-level cell region in the third mode.