IP Library Granted Patent US 11,003,582
Granted Patent B2
US 11,003,582 · App. 16/143,734 · Granted May 11, 2021

Cache utilization of backing storage for aggregate bandwidth

Inventors: Chace Clark (Hillsboro, TX); Francis Corrado (Newton, MA)
Assignee: Intel Corporation
G06F12/0888G06F3/061G06F3/0608G06F3/0625G06F3/0634G06F3/0653G06F3/0679G06F12/0804G06F12/0866G06F13/161G06F13/1642G06F2212/1024G06F2212/2022
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Quick Facts
Patent No.
US 11,003,582
App. No.
16/143,734
Granted
May 11, 2021
Kind
B2
Abstract

An embodiment of a semiconductor apparatus may include technology to determine workload-related information for a persistent storage media and a cache memory, and aggregate a bandwidth of the persistent storage media and the cache memory based on the determined workload information. Other embodiments are disclosed and claimed.

Claims (58)

1. A semiconductor apparatus for use with a persistent storage media and a cache memory, the semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:

determine workload-related information for the persistent storage media and the cache memory;

determine a first latency for an IO request to be serviced by the persistent storage media;

determine a second latency for the IO request to be serviced by the cache memory;

direct the IO request to either the persistent storage media or the cache memory based on the determined first and second latencies and a first IO request queue depth threshold, wherein the IO request is only sent to the persistent storage media or the cache memory with a lowest comparative latency between the first and second latencies when the first IO request queue depth threshold is exceeded, and wherein the IO request is sent to both the persistent storage media and the cache memory in parallel when the first IO request queue depth threshold is exceeded;

aggregate a bandwidth of the persistent storage media and the cache memory based on the determined workload information;

track whether the cache memory is bypassed due to aggregation of the bandwidth; and

promote IO requests from the persistent storage media to the cache memory at a later time in response to tracking whether the cache memory is bypassed and in response to a determination that the cache memory is underutilized.

2. The semiconductor apparatus for use with a persistent storage media and a cache memory of claim 1 , wherein the logic is further to:

send an overflow IO operation to the persistent storage media based on the determined workload-related information.

3. The semiconductor apparatus for use with a persistent storage media and a cache memory of claim 1 , wherein the logic is further to:

determine first load-related information for the persistent storage media;

determine second load-related information for the cache memory; and

determine whether to send the IO request to the cache memory or directly to the persistent storage media based on the determined first and second load-related information.

4. The semiconductor apparatus for use with a persistent storage media and a cache memory of claim 3 , wherein the logic is further to:

direct the IO request to either the persistent storage media or the cache memory based on an additive bandwidth and a second IO request queue depth threshold.

5. The semiconductor apparatus for use with a persistent storage media and a cache memory of claim 1 , wherein the cache memory comprises a write back cache memory.

6. The semiconductor apparatus for use with a persistent storage media and a cache memory of claim 1 , wherein the persistent storage media comprises a solid state drive.

7. The semiconductor apparatus for use with a persistent storage media and a cache memory of claim 1 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

8. An electronic storage system, comprising:

persistent storage media;

cache memory; and

logic communicatively coupled to the persistent storage media and the cache memory to:

determine workload-related information for the persistent storage media and the cache memory;

determine a first latency for an IO request to be serviced by the persistent storage media;

determine a second latency for the IO request to be serviced by the cache memory;

direct the IO request to either the persistent storage media or the cache memory based on the determined first and second latencies and a first IO request queue depth threshold, wherein the IO request is only sent to the persistent storage media or the cache memory with a lowest comparative latency between the first and second latencies when the first IO request queue depth threshold is not exceeded, and wherein the IO request is sent to both the persistent storage media and the cache memory in parallel when the first IO request queue depth threshold is exceeded;

aggregate a bandwidth of the persistent storage media and the cache memory based on the determined workload information;

track whether the cache memory is bypassed due to aggregation of the bandwidth; and

promote IO requests from the persistent storage media to the cache memory at a later time in response to tracking whether the cache memory is bypassed and in response to a determination that the cache memory is underutilized.

9. The electronic storage system of claim 8 , wherein the logic is further to:

send an overflow IO operation to the persistent storage media based on the determined workload-related information.

10. The electronic storage system of claim 8 , wherein the logic is further to:

determine first load-related information for the persistent storage media;

determine second load-related information for the cache memory; and

determine whether to send the TO request to the cache memory or directly to the persistent storage media based on the determined first and second load-related information.

11. The electronic storage system of claim 10 , wherein the logic is further to:

direct the TO request to either the persistent storage media or the cache memory based on an additive bandwidth and a second TO request queue depth threshold.

12. The electronic storage system of claim 8 , wherein the cache memory comprises a write back cache memory.

13. The electronic storage system of claim 8 , wherein the persistent storage media comprises a solid state drive.

14. A method of managing storage, comprising:

determining workload-related information for a persistent storage media and a cache memory;

determining a first latency for an TO request to be serviced by the persistent storage media;

determining a second latency for the TO request to be serviced by the cache memory;

directing the TO request to either the persistent storage media or the cache memory based on the determined first and second latencies and a first TO request queue depth threshold, wherein the TO request is only sent to the persistent storage media or the cache memory with a lowest comparative latency between the first and second latencies when the first TO request queue depth threshold is not exceeded, and wherein the TO request is sent to both the persistent storage media and the cache memory in parallel when the first TO request queue depth threshold is exceeded;

aggregating a bandwidth of the persistent storage media and the cache memory based on the determined workload information;

tracking whether the cache memory is bypassed due to aggregation of the bandwidth; and

promoting IO requests from the persistent storage media to the cache memory at a later time in response to tracking whether the cache memory is bypassed and in response to a determination that the cache memory is underutilized.

15. The method of claim 14 , further comprising:

sending an overflow IO operation to the persistent storage media based on the determined workload-related information.

16. The method of claim 14 , further comprising:

determining first load-related information for the persistent storage media;

determining second load-related information for the cache memory; and

determining whether to send the IO request to the cache memory or directly to the persistent storage media based on the determined first and second load-related information.

17. The method of claim 16 , further comprising:

directing the IO request to either the persistent storage media or the cache memory based on an additive bandwidth and a second IO request queue depth threshold.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2023
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 064928/0832 →
CORRECTIVE ASSIGNMENT TO CORRECT THE JORDAN IP LAW, LLC12501 PROSPERITY DRIVE, SUITE 401SILVER SPRING, MD 20904 PREVIOUSLY RECORDED ON REEL 047882 FRAME 0191. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 5, 2020
From: CLARK, CHACE; CORRADO, FRANCIS
To: INTEL CORPORATION
Reel/Frame 053414/0086 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2019
From: CLARK, CHACE; CORRADO, FRANCIS
To: INTEL CORPORATION
Reel/Frame 047882/0191 →