SSD having a parallelized, multi-level program voltage verification
An apparatus is described. The apparatus includes a storage device controller having logic circuitry to apply a program voltage verification process for a first threshold level to a group of non volatile memory cells and correlate first program voltages for the group of non volatile memory cells determined from the process to a second threshold level to determine second program voltages for the second threshold level for the group of non volatile memory cells. The second threshold level is higher than the first threshold level.
1. An apparatus, comprising:
a storage device controller comprising logic circuitry to apply a program voltage verification process for a first threshold level to a group of non volatile memory cells and correlate first program voltages for the group of non volatile memory cells determined from the process to a second threshold level to determine second program voltages for the second threshold level for the group of non volatile memory cells, wherein, the second threshold level is higher than the first threshold level.
2. The apparatus of claim 1 wherein the logic circuitry is also to apply the program voltage verification process for the first threshold level to another group of non volatile memory cells, wherein third program voltages determined from the process for the other group of non volatile memory are used to program the other group of non volatile memory cells from the first threshold level.
3. The apparatus of claim 2 wherein the process includes applying a same word line voltage to the group of non volatile memory cells and the other group of non volatile memory cells.
4. The apparatus of claim 2 wherein the process includes applying a same pass/fail test voltage to the group of non volatile memory cells and the other group of non volatile memory cells.
5. The apparatus of claim 2 wherein the logic circuitry is also to apply the program voltage verification process for the first threshold level to a third group of non volatile memory cells and correlate fourth program voltages for the third group of non volatile memory cells determined from the process to a third threshold level to determine fifth program voltages for the third threshold level for the third group of non volatile memory cells, wherein, the third threshold level is higher than the second threshold level.
6. The apparatus of claim 1 wherein the correlation is to add a fixed voltage amount to at least one of the first program voltages to determine a corresponding one of the second program voltages.
7. The apparatus of claim 1 wherein the correlation is to add different voltage amounts to certain ones of the first program voltages based on memory cell strength to determine corresponding ones of the second program voltages.
8. A computing system, comprising:
one or more processing cores;
a system memory;
a memory controller disposed between the system memory and the one or more processing cores;
a network interface;
a mass storage device comprising a controller, the controller comprising logic circuitry to apply a program voltage verification process for a first threshold level to a group of non volatile memory cells and correlate first program voltages for the group of non volatile memory cells determined from the process to a second threshold level to determine second program voltages for the second threshold level for the group of non volatile memory cells, wherein, the second threshold level is higher than the first threshold level.
9. The computing system of claim 8 wherein the logic circuitry is also to apply the program voltage verification process for the first threshold level to another group of non volatile memory cells, wherein third program voltages determined from the process for the other group of non volatile memory cells are used to program the other group of non volatile memory cells from the first threshold level.
10. The computing system of claim 9 wherein the process includes applying a same word line voltage to the group of non volatile memory cells and the other group of non volatile memory cells.
11. The computing system of claim 9 wherein the process includes applying a same pass/fail test voltage to the group of non volatile memory cells and the other group of non volatile memory cells.
12. The computing system of claim 9 wherein the logic circuitry is also to apply the program voltage verification process for the first threshold level to a third group of non volatile memory cells and correlate fourth program voltages for the third group of non volatile memory cells determined from the process to a third threshold level to determine fifth program voltages for the third threshold level for the third group of non volatile memory cells, wherein, the third threshold level is higher than the second threshold level.
13. The computing system of claim 8 wherein the correlation is to add a fixed voltage amount to at least one of the first program voltages to determine a corresponding one of the second program voltages.
14. The computing system of claim 8 wherein the correlation is to add different voltage amounts to certain ones of the first program voltages based on memory cell strength to determine corresponding ones of the second program voltages.
15. A method, comprising:
applying a program voltage verify process to both a first and second group of non volatile memory cells;
establishing program voltages of the program voltage verify process as appropriate program voltages for the first group of non volatile memory cells for a first threshold level;
determining appropriate program voltages for the second group of non volatile memory cells for a second threshold level by correlating to program voltages of the program voltage verify process that were applied to the second group of non volatile memory cells.
16. The method of claim 15 wherein the program voltage verification process applies a same word line voltage to both the first and second group of non volatile memory cells.
17. The method of claim 15 wherein the program voltage verification process applies a same pass/fail test voltage to both the first and second group of non volatile memory cells.
18. The method of claim 15 wherein the correlating comprises adding a fixed voltage amount to the program voltages of the program voltage verify process applied to the second group of non memory cells.
19. The method of claim 15 wherein the correlating comprises adding different voltage amounts to the program voltages of the program voltage verify process applied to the second group of non memory cells based on memory cell strength.
20. The method of claim 15 wherein the method further comprises:
applying the program voltage verify process to a third group of non volatile memory cells along with the first and second group of non volatile memory cells;
determining appropriate program voltages for the third group of non volatile memory cells for a third threshold level by correlating to program voltages of the program voltage verify process that were applied to the third group of non volatile memory cells.