IP Library Granted Patent US 7,737,031
Granted Patent B2
US 7,737,031 · App. 11/832,972 · Granted Jun 15, 2010

Insitu formation of inverse floating gate poly structures

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Quick Facts
Patent No.
US 7,737,031
App. No.
11/832,972
Granted
Jun 15, 2010
Kind
B2
Abstract

Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed.

Claims (15)

1. A method of making an inverse-t shaped floating gate in a non-volatile memory cell, comprising:

forming a tunnel oxide layer on a substrate;

depositing a first polysilicon layer over the layer of tunnel oxide, the first polysilicon layer comprising: undoped, p-doped or n-doped or combinations thereof;

depositing a second polysilicon layer over the first polysilicon layer, the second polysilicon layer comprising: p-doped or n-doped or combinations thereof, and the second polysilicon layer being more heavily doped than the first polysilicon layer;

applying a mask over the second polysilicon layer;

forming a trench at least partially extending through the first and second polysilicon layers and the tunnel oxide and the trench at least partially extending into the substrate;

stripping the mask from the second polysilicon layer and forming an oxide layer on a top surface and sidewalls of the second polysilicon layer during a controlled defume/strip process carried out in oxygen plasma; and

removing the oxide from the top surface and sidewalls of the second polysilicon layer.

2. The method of claim 1 , wherein removing the oxide from the top surface and sidewalls of the second polysilicon layer forms the inverse-t shaped floating gate.

3. The method of claim 2 , wherein the tunnel oxide layer has a depth of about 60-70 Å.

4. The method of claim 2 , wherein said forming a trench results in the trench having a depth of about 1500-2200 Å.

5. The method of claim 2 , wherein the trench is formed by shallow trench isolation performed at about 15-20 mTorr of pressure.

6. The method of claim 2 , wherein the mask is stripped and the oxide is formed at about 5 mTorr-20_mTorr.

7. The method of claim 2 , wherein the mask is stripped and the oxide is formed at about 5000_W-1000 W.

8. The method of claim 2 , wherein the mask is stripped and the oxide is formed at about 20_V-100_V.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2023
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 064928/0832 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2008
From: ALAPATI, RAMAKANTH; SANDHU, GURTEJ
To: INTEL CORPORATION
Reel/Frame 021723/0187 →