Vertical memory device and method
View Patent ↗Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate.
1. A memory cell, comprising:
a substrate;
a body extending vertically from said substrate;
a first gate comprising a vertical member and a horizontal member, wherein said first gate is disposed laterally from said body; and
a second gate comprising a vertical member and a horizontal member, wherein said second gate is disposed laterally from said first gate.
2. The memory cell of claim 1 , wherein said first and second gates comprise polysilicon.
3. The memory cell of claim 1 , further comprising a first dielectric formed between said first gate and said body.
4. The memory cell of claim 3 , wherein said first dielectric comprises a vertical portion having a first thickness adjacent to said body and a horizontal portion having a second thickness adjacent to said substrate, wherein said second thickness is greater than said first thickness.
5. The memory cell of claim 4 , wherein said first dielectric comprises an oxide.
6. The memory cell of claim 3 , further comprising a second dielectric between said first and second gates.
7. The memory cell of claim 6 , wherein said second dielectric comprises an oxide-nitride-oxide.
8. The memory cell of claim 1 , wherein a capacitive coupling ratio between said first and second gates is between 0.3 and 0.6.
9. A memory array, comprising:
multiple memory cells, wherein each of said cells comprises a substrate; a body extending vertically from said substrate, a source, and a drain; a first gate comprising a vertical member and a horizontal member, wherein said first gate is disposed laterally from said body; and a second gate comprising a vertical member and a horizontal member, wherein said second gate is disposed laterally from said first gate;
multiple gate lines interconnecting said second gates of each of said memory cells;
multiple drain lines interconnecting said drains of each of said memory cells; and
multiple source lines interconnecting said sources of each of said memory cells.
10. The memory away of claim 9 , wherein said first and second gates comprise polysilicon.
11. The memory away of claim 9 , further comprising a first dielectric formed between said first gate and said body.
12. The memory away of claim 11 , wherein said first dielectric comprises a vertical portion having a first thickness adjacent to said body and a horizontal portion having a second thickness adjacent to said substrate, wherein said second thickness is greater than said first thickness.
13. The memory away of claim 9 , wherein a capacitive coupling ratio between said first and second gates is between 0.3 and 0.6.
14. An apparatus, comprising:
a random access memory comprising multiple memory cells;
wherein each of said memory cells comprises:
a substrate;
a body extending vertically from said substrate;
a first gate comprising a vertical member and a horizontal member, wherein said first gate is disposed laterally from said body; and
a second gate comprising a vertical member and a horizontal member, wherein said second gate is disposed laterally from said first gate.
15. The apparatus of claim 14 , wherein the random access memory is a dynamic random access memory.
16. The apparatus of claim 14 , wherein the random access memory is a static random access memory.
17. The apparatus of claim 14 , wherein the random access memory is a synchronous random access memory.