IP Library Granted Patent US 11,018,149
Granted Patent B2
US 11,018,149 · App. 14/228,247 · Granted May 25, 2021

Building stacked hollow channels for a three dimensional circuit device

Inventors: Zhenyu Lu (Boise, ID); Roger Linsday (Boise, ID); Sergei V Koveshnikov (Boise, ID)
Assignee: Intel Corporation
H01L27/11582H01L27/1157H01L27/11556
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,018,149
App. No.
14/228,247
Granted
May 25, 2021
Kind
B2
Abstract

A three dimensional stacked circuit device includes multiple decks of circuit elements, each deck including multiple tiers of circuit elements. Each deck includes a highly doped hollow channel extending through the deck. Below the first deck is a source conductor to drive activity of the circuit elements. Between each deck is a conductive stop layer that interconnects the hollow channel from one deck to the hollow channel of the deck adjacent to it. Thus, all hollow channels of all decks are electrically coupled to the source conductor.

Claims (7)

1. A circuit device comprising:

multiple decks of memory cells, the decks being stacked on each other, wherein a deck includes:

multiple tiers of memory cells stacked on each other; and

at least one channel extending through the deck, the channel including a channel insulator, and a doped polycrystalline material surrounding the channel insulator at an end of the channel and positioned between the multiple tiers of memory cells and the channel insulator;

a conductive stop layer between a channel of a given deck and a channel of an adjacent deck, wherein the conductive stop layer is located over and completely covers the doped polycrystalline material and channel insulator of the channel of the given deck, and wherein the conductive stop layer is located under the doped polycrystalline material surrounding the channel insulator at the end of the channel of the adjacent deck; and

an insulating layer between the given deck and the adjacent deck, wherein the insulating layer is thicker than an insulating layer between two adjacent tiers of memory cells, and wherein the insulating layer is at least partially over and in contact with a top surface of the conductive stop layer near sides of the conductive stop layer;

wherein a region of the insulating layer between the given deck and the adjacent deck is between the top surface of the conductive stop layer and the doped polycrystalline material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2023
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 064928/0832 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2014
From: LU, ZHENYU; LINDSAY, ROGER; KOVESHNIKOV, SERGEI
To: INTEL CORPORATION
Reel/Frame 033164/0162 →