IP Library › Granted Patent US 8,208,305

Granted Patent B2

US 8,208,305 · App. 12/655,157 · Granted Jun 26, 2012

Arrangement of pairs of NAND strings that share bitline contacts while utilizing distinct sources lines

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Quick Facts

Patent No.: US 8,208,305
App. No.: 12/655,157
Granted: Jun 26, 2012
Kind: B2

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USPTO Patent Center↗ Full Patent PDF↗

Abstract

A non-volatile microelectronic memory that has a memory cell array, which includes memory cell string pairs that share a bitline contact, that have separate source lines, and that have at least two transistors within each memory cell string that may be programming for sharing the bitline contact.

Claims (96)

1. A memory cell array, comprising:

a bitline contact connected to a first memory cell string and a second memory cell string;

the first memory cell string including at least first and second dummy memory cells adapted to be programmed to share the bitline contact;

the second memory cell string including at least first and second dummy memory cells adapted to be programmed to share the bitline contact;

a first source line connected to the first memory cell string; and

a second source line connected to the second memory cell string;

wherein the first dummy memory cell of the first memory cell string and the second dummy memory cell of the second memory cell string are programmed in the following sequence:

performing a coarse program operation to the first dummy memory cell of the first memory cell string;

performing a coarse program operation to the second dummy memory cell of the second memory cell string;

performing a fine program operation to the first dummy memory cell of the first string;

performing a program verify operation on the first dummy memory cell of the first string

performing a fine program operation to the second dummy memory cell of the second string; and

performing a program verify operation on the second dummy memory cell of the second string.

2. The memory cell array of claim 1 , wherein the first memory cell string further comprises at least two ground selection transistors, and wherein the second memory cell string further comprises at least two ground selection transistors.

3. A memory cell array, comprising:

a first memory cell string including at least two dummy memory cells;

a second memory cell string including at least two dummy memory cells;

a first bitline contact connected to the first memory cell string and the second memory cell string;

a first source line connected to the first memory cell string;

a second source line connected to the second memory cell string;

wherein a dummy memory cell of the first memory cell string and a dummy memory cell of the second memory cell string are programmed in the following sequence:

performing a coarse program operation to the dummy memory cell of the first memory cell string;

performing a coarse program operation to the dummy memory cell of the second memory cell string;

performing a fine program operation to the dummy memory cell of the first string;

performing a program verify operation on the dummy memory cell of the first string

performing a fine program operation to the dummy memory cell of the second string; and

performing a program verify operation on the dummy memory cell of the second string.

4. The memory cell array of claim 3 , wherein a first dummy memory cell of the first memory cell string is connected to a first dummy memory cell of the second memory cell string.

5. The memory cell array of claim 4 , wherein a threshold voltage of the first dummy memory cell of the first memory cell string is programmed to a different threshold voltage than the first dummy memory cell of the second memory cell string.

6. The memory cell array of claim 3 , wherein a second dummy memory cell of the first memory cell string is connected to a second dummy memory cell of the second memory cell string.

7. The memory cell array of claim 6 , wherein a threshold voltage of the second dummy memory cell of the first memory cell string is programmed to a different threshold voltage than the second dummy memory cell of the second memory cell string.

8. The memory cell array of claim 3 , comprising:

a third memory cell string including at least two dummy memory cells;

a fourth memory cell string including at least two dummy memory cells;

a second bitline contact connected to the third memory cell string and the fourth memory cell string;

the first source line connected to the fourth memory cell string; and

the second source line connected to the third memory cell string.

9. A memory cell array, comprising:

a first memory cell string including at least two ground selection transistors;

a second memory cell string including at least two ground selection transistors;

a first bitline contact connected to the first memory cell string and the second memory cell string;

a first source line connected to the first memory cell string;

a second source line connected to the second memory cell string;

wherein a ground selection transistor of the first memory cell string and a ground selection transistor of the second memory cell string are programmed in the following sequence:

performing a coarse program operation to the ground selection transistor of the first memory cell string;

performing a coarse program operation to the ground selection transistor of the second memory cell string;

performing a fine program operation to the ground selection transistor of the first string;

performing a program verify operation on the ground selection transistor of the first string;

performing a fine program operation to the round selection transistor of the second string; and

performing a program verify operation on the ground selection transistor of the second string.

10. The memory cell array of claim 9 , wherein a first ground selection transistor of the first memory cell string is connected to a first ground selection transistor of the second memory cell string.

11. The memory cell array of claim 10 , wherein a threshold voltage of the first ground selection transistor of the first memory cell string is programmed to a different threshold voltage than the first ground selection transistor of the second memory cell string.

12. The memory cell array of claim 9 , wherein a second ground selection transistor of the first memory cell string is electrically coupled to a second ground selection transistor of the second memory cell string.

13. The memory cell array of claim 12 , wherein a threshold voltage of the second ground selection transistor of the first memory cell string is programmed to a different threshold voltage than the second ground selection transistor of the second memory cell string.

14. The memory cell array of claim 9 , comprising:

a third memory cell string including at least two ground selection transistors;

a fourth memory cell string including at least two ground selection transistors;

a second bitline contact connected to the third memory cell string and the fourth memory cell string;

the first source line connected to the fourth memory cell string;

and the second source line connected to the third memory cell string.

15. An electronic system, comprising:

a processor; and

a memory device in data communication with the processor, the memory device comprising memory cell array including:

a first bitline contact connected to a first memory cell string and a second memory cell string;

the first memory cell string including at least first and second dummy memory cells adapted to be programmed to share the first bitline contact;

the second memory cell string including at least first and second dummy memory cells adapted to be programmed to share the first bitline contact and a first memory cell coupled to the first word line;

a first source line connected to the first memory cell string; and

a second source line connected to the second memory cell string;

wherein the first dummy memory cell of the first memory cell string and the second dummy memory cell of the second memory cell string are programmed in the following sequence:

performing a coarse program operation to the first dummy memory cell of the first memory cell string;

performing a coarse program operation to the second dummy memory cell of the second memory cell string;

performing a fine program operation to the first dummy memory cell of the first string;

performing a program verify operation on the first dummy memory cell of the first string;

performing a fine program operation to the second dummy memory cell of the second string; and

performing a program verify operation on the second dummy memory cell of the second string.

16. The electronic system of claim 15 , wherein the first dummy memory cell of the first memory cell string is connected to the first dummy memory cell of the second memory cell string.

17. The electronic system of claim 16 , wherein the threshold voltage of the first dummy memory cell of the first memory cell string is adapted to be programmed to a different threshold voltage than the first dummy memory cell of the second memory cell string.

18. The electronic system of claim 15 , wherein the second dummy memory cell of the first memory cell string is connected to the second dummy memory cell of the second memory cell string.

19. The electronic system of claim 18 , wherein a threshold voltage of the second dummy memory cell of the first memory cell string is programmed to a different threshold voltage than the second dummy memory cell of the second memory cell string.

20. The electronic system of claim 15 , comprising:

a third memory cell string including a plurality of memory cells and at least two dummy memory cells;

a fourth memory cell string including a plurality of memory cells and at least two dummy cells;

a second bitline contact connected to the third memory cell string and the fourth memory cell string;

the first source line connected to the fourth memory cell string; and

the second source line connected to the third memory cell string.

21. The electronic system of claim 15 , wherein the first memory cell string further comprises at least two ground selection transistors, and wherein the second memory cell string further comprises at least two ground selection transistors.

22. The electronic system of claim 21 , wherein a first ground selection transistor of the first memory cell string is connected to a first ground selection transistor of the second memory cell string.

23. The electronic system of claim 22 , wherein a threshold voltage of the first ground selection transistor of the first memory cell string is programmed to a different threshold voltage than the first ground selection transistor of the second memory cell string.

24. The electronic system of claim 21 , wherein a second ground selection transistor of the first memory cell string is connected to a second ground selection transistor of the second memory cell string.

25. The electronic system of claim 24 , wherein a threshold voltage of the second ground selection transistor of the first memory cell string is programmed to a different threshold voltage than the second ground selection transistor of the second memory cell string.

26. The electronic system of claim 21 , comprising:

a third memory cell string including at least two ground selection transistors;

a fourth memory cell string including at least two ground selection transistors;

a second bitline contact connected to the third memory cell string and the fourth memory cell string;

the first source line connected to the fourth memory cell string; and

the second source line connected to the third memory cell string.

Assignments (2)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2023

From: INTEL CORPORATION

To: INTEL NDTM US LLC

Reel/Frame 064928/0832 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2012

From: TANZAWA, TORU

To: INTEL CORPORATION

Reel/Frame 028076/0804 →