Erase and soft program for vertical NAND flash

1. A method comprising:

causing an erase cycle on a selected block of NAND memory that includes two or more sub-blocks;

determining a subset of the two or more sub-blocks by:

checking threshold voltages of the two or more sub-blocks against a target maximum voltage; and

including sub-blocks that have a threshold voltage higher than the target maximum voltage in the subset;

verifying the two or more sub-blocks in the subset until a sub-block fails to verify;

stopping the verification in response to the failed verify;

causing another erase cycle on the selected block of NAND memory; and

re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.

2. The method of claim 1 , further comprising:

(a) stopping the re-started verify in response to another failure to verify a sub-block;

(b) causing another erase cycle on the selected block of NAND memory;

(c) re-starting to verify the two or more sub-blocks at a sub-block that last failed to verify; and

repeating (a), (b) and (c) until no sub-blocks in the selected block of NAND memory fail to verify.

3. The method of claim 1 , further comprising:

causing a soft program cycle on the selected block of NAND memory;

determining an other subset of the two or more sub-blocks;

validating sub-blocks of the other subset;

executing an other soft program cycle on the selected block of NAND memory if none of the sub-blocks of the other subset passes validation;

repeating said validating and said executing until at least one of the sub-blocks of the other subset passes validation; and

re-verifying the two or more sub-blocks.

4. The method of claim 3 , wherein the other subset includes a last sub-block to verify.

5. The method of claim 1 , wherein the two or more sub-blocks are verified serially.

6. The method of claim 1 , further comprising programming one or more dummy cells of the two or more sub-blocks of the selected block of NAND memory to have a positive threshold voltage.

7. An apparatus comprising:

a block of NAND memory comprising two or more sub-blocks coupled to a bit line, a sub-block comprising a vertical NAND string of two or more memory cells coupled to the bit line; and

circuitry coupled to the block of NAND memory, the circuitry being configured to:

execute an erase cycle on the block of NAND memory;

check threshold voltages of the two or more sub-blocks against a target maximum voltage;

include sub-blocks that have a threshold voltage higher than the target maximum voltage in a subset of the two or more sub-blocks;

verify the two or more sub-blocks until a sub-block fails to verify;

stop the verification in response to the failed verify;

cause an other erase cycle on the block of NAND memory;

re-start to verify the two or more sub-blocks at the sub-block that failed to verify; and

repeat said stop, said cause and said re-start until no sub-blocks in the block of NAND memory fail to verify.

8. The apparatus of claim 7 , the circuitry further configured to:

cause a soft program cycle on the block of NAND memory;

determine an other subset of the two or more sub-blocks;

validate the sub-blocks of the other subset;

execute an other soft program cycle on the block of NAND memory if none of the sub-blocks of the other subset passes validation;

repeat the validation and the execution until at least one of the sub-blocks of the other subset passes validation; and

re-verify the two or more sub-blocks.

9. The apparatus of claim 8 , wherein the other subset includes a last sub-block to verify.

10. The apparatus of claim 7 , the circuitry further configured to:

program one or more dummy cells of the two or more sub-blocks of the block of NAND memory to have a positive threshold voltage;

wherein a sub-block comprises:

at least a first dummy cell included at one end of the NAND string; and

at least a second dummy cell included at the other end of the NAND string.

11. The apparatus of claim 7 , further comprising supervisor circuitry including a controller interface coupled to a memory interface to send commands and exchange data compliant with a memory access protocol that is compliant, at least in part, with an Open NAND Flash Interface (ONFI) specification.

12. The apparatus of claim 7 , wherein the apparatus is a solid state drive.

13. An apparatus comprising:

a block of NAND memory comprising two or more sub-blocks coupled to a bit line, a sub-block comprising a vertical NAND string of two or more memory cells coupled to the bit line; and

circuitry coupled to the block of NAND memory, the circuitry being configured to:

erase the block of NAND memory;

check threshold voltages of the two or more sub-blocks against a target maximum voltage;

include sub-blocks that have a threshold voltage higher than the target maximum voltage in a subset of the two or more sub-blocks;

verify the sub-blocks in the subset until a sub-block fails to verify;

cause a soft program cycle on the block of NAND memory;

determine an other subset of the two or more sub-blocks;

validate sub-blocks of the other subset;

execute an other soft program cycle on the block of NAND memory if none of the sub-blocks of the other subset passes validation;

repeat said validation and said execution until at least one of the sub-blocks of the subset passes validation; and

re-verify the two or more sub-blocks.

14. The apparatus of claim 13 , the circuitry further configured to:

stop the verification or the re-verification in response to a failure to verify a sub-block of the subset or a sub-block of the other subset;

cause another erase cycle on the block of NAND memory; and

re-start to verify the two or more sub-blocks at the sub-block of the subset or the sub-block of the other subset that failed to verify.

15. The apparatus of claim 13 , the circuitry further configured to:

(a) validate sub-blocks of the subset again;

(b) cause an other soft program cycle on the block of NAND memory; and

repeat (a) and (b) until all of the sub-blocks of the subset pass validation;

wherein (a) skips a sub-block after the sub-block has passed validation.

16. The apparatus of claim 13 , the circuitry further configured to:

program one or more dummy cells of the two or more sub-blocks of the block of NAND memory to have a positive threshold voltage;

wherein a sub-block comprises:

at least a first dummy cell included at one end of the vertical NAND string; and

at least a second dummy cell included at the other end of the vertical NAND string.

17. The apparatus of claim 13 , wherein the apparatus is a solid state drive.