IP Library Granted Patent US 10,290,356
Granted Patent B2
US 10,290,356 · App. 15/050,871 · Granted May 14, 2019

Erase and soft program for vertical NAND flash

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Quick Facts
Patent No.
US 10,290,356
App. No.
15/050,871
Granted
May 14, 2019
Kind
B2
Abstract

Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.

Claims (20)

1. A method comprising:

erasing a selected block of NAND memory comprising two or more sub-blocks;

performing a soft program cycle on the selected block of NAND memory;

determining a subset of the two or more sub-blocks;

validating sub-blocks of the subset by:

checking threshold voltages of the two or more sub-blocks against a target minimum voltage; and

including sub-blocks that have a threshold voltage lower than the target minimum voltage in the subset;

executing an other soft program cycle on the selected block of NAND memory if none of the sub-blocks of the subset pass validation;

repeating said validating and said executing until at least one of the sub-blocks of the subset passes validation;

verifying the two or more sub-blocks in the subset until a sub-block fails to verify;

stopping the verification in response to the failed verify;

performing another erase cycle on all of the selected block of NAND memory; and

re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.

2. The method of claim 1 , wherein the sub-blocks of the subset are validated serially.

3. The method of claim 1 , further comprising:

(a) validating the sub-blocks of the subset again;

(b) performing an other soft program cycle on the selected block of NAND memory; and

repeating (a) and (b) until all of the sub-blocks of the subset pass validation;

wherein said (a) validating the sub-blocks of the subset again skips a sub-block after a sub-block being validated has passed validation.

4. The method of claim 1 , further comprising programming one or more dummy cells of the two or more sub-blocks of the selected block of NAND memory to have a positive threshold voltage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2023
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 064928/0832 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2017
From: PARAT, KRISHNA K.; KALAVADE, PRANAV; KAWAI, KOICHI; GODA, AKIRA
To: INTEL CORPORATION
Reel/Frame 041852/0831 →