Erase and soft program for vertical NAND flash

1. A method to erase a block of NAND memory comprising:

performing an erase cycle on a selected block of NAND memory comprising two or more sub-blocks;

determining a subset of the two or more sub-blocks by:

checking threshold voltages of the two or more sub-blocks against a target maximum voltage; and

including sub-blocks that have a threshold voltage higher than the target maximum voltage in said subset;

verifying the two or more sub-blocks in the subset until a sub-block fails to verify;

stopping the verification in response to the failed verify;

performing another erase cycle on the selected block of NAND memory; and

re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.

2. The method of claim 1 , further comprising:

(a) stopping the re-started verify in response to another failure to verify a sub-block;

(b) performing another erase cycle on the selected block of NAND memory;

(c) re-starting to verify the two or more sub-blocks at a sub-block that last failed to verify; and

repeating (a), (b) and (c) until no sub-blocks in the selected block of NAND memory fail to verify.

3. The method of claim 1 , further comprising:

performing a soft program cycle on the selected block of NAND memory;

determining another subset of the two or more sub-blocks;

validating sub-blocks of said another subset;

executing another soft program cycle on the selected block of NAND memory if none of the sub-blocks of said another subset passes validation;

repeating said validating and said executing until at least one of the sub-blocks of said another subset passes validation; and

re-verifying the two or more sub-blocks.

4. The method of claim 3 , wherein said other subset includes a last sub-block to verify.

5. The method of claim 1 , wherein the two or more sub-blocks are verified serially.

6. The method of claim 1 , further comprising programming one or more dummy cells of the two or more sub-blocks of the selected block of NAND memory to have a positive threshold voltage.

7. A method to erase a block of NAND memory comprising:

erasing a selected block of NAND memory comprising two or more sub-blocks;

performing a soft program cycle on the selected block of NAND memory;

determining a subset of the two or more sub-blocks, by:

checking threshold voltages of the two or more sub-blocks against a target maximum voltage; and

including sub-blocks that have a threshold voltage higher than the target maximum voltage in said subset;

validating sub-blocks of said subset;

executing another soft program cycle on the selected block of NAND memory if none of the sub-blocks of said subset pass validation; and

repeating said validating and said executing until at least one of the sub-blocks of said subset passes validation.

8. The method of claim 7 , wherein the sub-blocks of said subset are validated serially.

9. The method of claim 7 , further comprising verifying the two or more sub-blocks.

10. The method of claim 7 , further comprising:

(a) validating the sub-blocks of said subset again;

(b) performing another soft program cycle on the selected block of NAND memory; and

repeating (a) and (b) until all of the sub-blocks of said subset pass validation;

wherein said (a) validating the sub-blocks of said subset again skips a sub-block after a sub-block being validated has passed validation.

11. The method of claim 7 , further comprising programming one or more dummy cells of the two or more sub-blocks of the selected block of NAND memory to have a positive threshold voltage.

12. An electronic apparatus comprising:

a block of NAND memory comprising two or more sub-blocks coupled to a bit line, a sub-block comprising a NAND string of two or more memory cells coupled to the bit line; and

circuitry coupled to the block of NAND memory, the circuitry being configured to:

execute an erase cycle on the block of NAND memory;

check threshold voltages of the two or more sub-blocks against a target maximum voltage; and

include sub-blocks that have a threshold voltage higher than the target maximum voltage in a subset;

verify the two or more sub-blocks in the subset until a sub-block fails to verify;

stop the verification in response to the failed verify;

perform another erase cycle on the block of NAND memory;

re-start to verify the two or more sub-blocks at the sub-block that failed to verify; and

repeat said stop, said perform and said re-start until no sub-blocks in the block of NAND memory fail to verify.

13. The electronic apparatus of claim 12 , the circuitry further configured to:

perform a soft program cycle on the block of NAND memory;

determine another subset of the two or more sub-blocks;

validate the sub-blocks of said another subset;

execute another soft program cycle on the block of NAND memory if none of the sub-blocks of said another subset passes validation;

repeat the validation and the execution until at least one of the sub-blocks of said another subset passes validation; and

re-verify the two or more sub-blocks.

14. The electronic apparatus of claim 13 , wherein said another subset includes a last sub-block to verify.

15. The electronic apparatus of claim 12 , the circuitry further configured to:

program one or more dummy cells of the two or more sub-blocks of the block of NAND memory to have a positive threshold voltage;

wherein a sub-block comprises:

at least a first dummy cell included at one end of said NAND string; and

at least a second dummy cell included at the other end of said NAND string.

16. The electronic apparatus of claim 12 , further comprising supervisor circuitry comprising a controller interface, coupled to the memory interface, to send commands and exchange data compliant with a memory access protocol, wherein the memory access protocol is compliant, at least in part, with an Open NAND Flash Interface (ONFI) specification.

17. The electronic apparatus of claim 12 , wherein the electronic apparatus is a solid state drive.

18. An electronic apparatus comprising:

a block of NAND memory comprising two or more sub-blocks coupled to a bit line, a sub-block comprising a NAND string of two or more memory cells coupled to the bit line; and circuitry coupled to the block of NAND memory, the circuitry being configured to:

erase the block of NAND memory;

check threshold voltages of the two or more sub-blocks against a target maximum voltage; and

include sub-blocks that have a threshold voltage higher than the target maximum voltage in a subset;

verify the two or more sub-blocks in the subset until a sub-block fails to verify;

perform a soft program cycle on the block of NAND memory;

determine a subset of the two or more sub-blocks;

validate sub-blocks of said subset;

execute another soft program cycle on the block of NAND memory if none of the sub-blocks of said subset passes validation; and

repeat said validation and said execution until at least one of the sub-blocks of said subset passes validation.

19. The electronic apparatus of claim 18 , the circuitry further configured to verify the two or more sub-blocks.

20. The electronic apparatus of claim 18 , the circuitry further configured to:

(a) validate sub-blocks of said subset again;

(b) perform another soft program cycle on the block of NAND memory; and

repeat (a) and (b) until all of the sub-blocks of said subset pass validation;

wherein (a) skips a sub-block after the sub-block has passed validation.

21. The electronic apparatus of claim 18 , the circuitry further configured to:

program one or more dummy cells of the two or more sub-blocks of the block of NAND memory to have a positive threshold voltage;

wherein a sub-block comprises:

at least a first dummy cell included at one end of said NAND string; and

at least a second dummy cell included at the other end of said NAND string.

22. The electronic apparatus of claim 18 , wherein the electronic apparatus is a solid state drive.