Isolated P-well architecture for a memory device
View Patent ↗A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to corresponding bitlines, which may be selected or inhibited, and may be at different voltages. During erase, read, and verify operations, the isolated P-wells may be coupled to source.
1. A memory device, comprising:
a memory array comprising memory cells arranged in a first string and a second string, the first string coupled to a first P-well and the second string coupled to a second P-well, wherein the first P-well is isolated from the second P-well, wherein the first P-well is capable of being biased to a voltage different from the voltage of the second P-well, and wherein the first P-well is biased to approximately Vcc or higher and the second P-well is biased to ground.
2. The memory device of claim 1 , wherein the first P-well is coupled to a first corresponding bitline and the second P-well is coupled to a second corresponding bitline.
3. The memory device of claim 2 , further comprising a first contact capable of coupling the first P-well to the first corresponding bitline.
4. The memory device of claim 3 , further comprising a second contact capable of coupling the second P-well to the second corresponding bitline.
5. The memory device of claim 2 , further comprising a first select gate capable of coupling of the first P-well with the first corresponding bitline and coupling of the second P-well with the second corresponding bitline.
6. The memory device of claim 5 , wherein coupling of the first P-well to the first corresponding bitline and the second P-well to the second corresponding bitline occurs during a program operation.
7. The memory device of claim 6 further comprising a second select gate capable of coupling of the first P-well and the second P-well to source.
8. The memory device of claim 1 , wherein during an erase operation, the first P-well and the second P-well are coupled to source.
9. The memory device of claim 8 , wherein source is biased to a predetermined erase voltage.
10. The memory device of claim 1 , wherein the voltage applied to the first P-well reduces reverse bias between a channel-source-drain region of the first string and a first P-well junction.
11. The memory device of claim 1 , wherein the first P-well is adjacent to the second P-well.
12. A memory device, comprising:
a NAND memory array comprising a first NAND string coupled to a first P-well and a second NAND string coupled to a second P-well, wherein the first P-well is capable of being biased to a voltage different from the voltage of the second P-well, and wherein the first P-well is biased to approximately Vcc or higher and the second P-well is biased to ground;
a first select gate capable of coupling the first P-well with a first bitline and the second P-well with a second bitline; and
a second select gate capable of coupling the first P-well and the second P-well to source.
13. The memory device of claim 12 , further comprising a first contact coupling the first P-well to the first bitline and a second contact coupling the second P-well to the second bitline.
14. The memory device of claim 12 , wherein the first bitline comprises an inhibited bitline and the second bitline comprises a selected bitline.
15. The memory device of claim 12 , wherein the voltage applied to the first P-well reduces reverse bias between a channel-source-drain region of the first string and a first P-well junction.