Method, system, and apparatus for ECC protection of small data structures
View Patent ↗Data structures of different sizes may be stored in memory using different ECC schemes. A memory device may include multiple ECC engines to support error correction operations on different sized data structures.
1. An apparatus comprising:
a memory array;
a first error correcting code (ECC) engine coupled to the memory array to perform ECC encoding and ECC decoding for data structures of a first size; and
a second ECC engine coupled to the memory array to perform ECC encoding and ECC decoding for data structures of a second size, wherein the data structures of the second size are larger than the data structures of the first size and wherein only one of said first and second ECC engines is operable at any time, the first error correcting code engine being operable when data structures of a first size are being written and said second ECC engine being operable when data structures of said second size are being written to the memory array.
2. The apparatus of claim 1 , wherein the data structures of the first size are four bits long.
3. The apparatus of claim 2 , wherein the data structures of the second size are 256 bits long.
4. The apparatus of claim 1 , wherein the memory array is comprised of a plurality of memory cells, each memory cell capable of storing two bits per cell.
5. The apparatus of claim 4 , wherein the first ECC engine is capable of correcting one cell error per four cell codeword.
6. The apparatus of claim 5 , wherein the first ECC engine is to utilize an encoding scheme having a plurality of codewords, each codeword comprised of a user data value and a parity data value, wherein the user data value matches the parity data value for at least two of the plurality of codewords.
7. The apparatus of claim 5 , wherein the second ECC engine is capable of correcting one cell error per 133 cell codeword.
8. A method comprising:
determining a size of a value to be written to a memory array;
using a first error correcting code (ECC) scheme if the value is of a first size; and
using a second ECC scheme if the value is of a second size, said first and second sizes being different.
9. The method of claim 8 , wherein the memory array is an array of nonvolatile memory cells.
10. The method of claim 8 , wherein writing the value to the memory array using the first ECC scheme comprises writing the value using a control mode.
11. The method of claim 10 , wherein the first ECC scheme is a quaternary ECC scheme capable of correcting one cell error per nibble.
12. The method of claim 8 , wherein writing the value to the memory array using the second ECC scheme comprises writing the value using an object mode.
13. The method of claim 12 , wherein the second ECC scheme is a quaternary ECC scheme capable of correcting one cell error per codeword.
14. A system comprising:
an interconnect;
a controller coupled to the interconnect; and
a memory device coupled to the interconnect, wherein the memory device includes a memory array, a first error correcting code (ECC) engine coupled to the memory array to perform ECC encoding and ECC decoding for data structures of a first size, and a second ECC engine coupled to the memory array to perform ECC encoding and ECC decoding for data structures of a second size, wherein the data structures of the second size are larger than the data structures of the first size and wherein only one of said first and second ECC engines is operable at any time, the first error correcting code engine being operable when data structures of a first size are being written and said second ECC engine being operable when data structures of said second size are being written to the memory array.
15. The system of claim 14 , wherein the memory device is a flash memory device and wherein the memory array is comprised of a plurality of memory cells, each memory cell capable of storing two bits per cell.
16. The system of claim 14 , wherein the data structures of the first size are four bits long.
17. The system of claim 16 , wherein the data structures of the second size are 256 bits long.
18. The system of claim 14 , wherein the first ECC engine is capable of correcting one cell error per four cell codeword and the second ECC engine is capable of correcting one cell error per 133 cell codeword.