Resistance reduction for word lines in memory arrays

1. An apparatus comprising:

a plurality of word lines of a memory array, wherein a word line includes a first word line plate and a second word line plate that are co-planar with one another and separated from one another by a slit such that the first word line plate is not directly physically coupled with the second word line plate, wherein the first word line plate forms a substantially rectangular shape that extends in an X direction and comprises a first material with a first resistivity, wherein an edge of the rectangular shape of the first word line plate is recessed and filled with a second material that has a second resistivity that is lower than the first resistivity to reduce total resistance of the first word line plate, wherein the first material is in direct physical contact with the second material and wherein the slit is filled with an insulating material that is in direct contact with the second material; and

a plurality of pillars disposed to intersect with the plurality of word lines in a Y direction that is orthogonal to the X direction in which the first word line plate forms the substantially rectangular shape, wherein a pillar of the plurality of pillars is in direct physical contact with the first material with the first resistivity of the first word line plate at an intersection of the pillar with the first word line plate.

2. The apparatus of claim 1 , wherein the first material includes polysilicon, and the second material includes a metal.

3. The apparatus of claim 1 , wherein the pillar of the plurality of pillars includes a number of storage cells, a storage cell includes a channel trapping layer surrounded by the word line, and a cell channel region surrounded by the channel trapping layer.

4. The apparatus of claim 3 , wherein the storage cell includes a floating gate transistor.

5. The apparatus of claim 3 , wherein the channel trapping layer includes an Oxide-Nitride-Oxide (ONO) material.

6. The apparatus of claim 3 , wherein the storage cell further includes an oxide material surrounded by the cell channel region.

7. The apparatus of claim 1 , wherein the memory array further includes a plurality of slits through the plurality of word lines, and wherein storage cells within the first word line plate form a first memory block, and storage cells within the second word line plate form a second memory block.

8. The apparatus of claim 1 , wherein the memory array further includes a source side select (SGS) transistor or a drain side select (SGD) transistor above or below the plurality of word lines.

9. The apparatus of claim 1 , wherein the memory array further includes a plurality of bit lines coupled to the plurality of pillars in a direction orthogonal to the plurality of word lines and the plurality of pillars.

10. A method for forming a memory array, the method comprising:

forming a plurality of word lines, wherein a word line includes a first word line plate and a second word line plate that are co-planar with one another and separated from one another by a slit such that the first word line plate is not directly physically coupled with the second word line plate, wherein the first word line plate includes a first material with a first resistivity, and the first word line plate forms a substantially rectangular shape that extends in an X direction;

forming a recess along an edge of the first word line plate;

filling the recess with a second material that has a second resistivity that is lower than the first resistivity to reduce total resistance of the word line, wherein the first material of the first word line plate is in direct physical contact with the second material of the first word line plate;

filling the slit with an insulating material that is in direct contact with the second material of the first word line plate; and

disposing a plurality of pillars to intersect with the plurality of word lines in a Y direction that is orthogonal to the X direction in which the first word line plate forms the substantially rectangular shape, wherein a pillar of the plurality of pillars is in direct physical contact with the first material at an intersection of the pillar with the first word line plate.

11. The method of claim 10 , wherein the first material includes polysilicon, and the second material includes a metal.

12. The method of claim 10 ,

wherein the pillar of the plurality of pillars includes a number of storage cells, a storage cell includes a channel trapping layer surrounded by the word line, and a cell channel region surrounded by the channel trapping layer.

13. The method of claim 10 , further comprising:

forming one or more dummy pillars disposed through the plurality of word lines, wherein a dummy pillar does not include a storage cell.

14. The method of claim 10 , forming a plurality of slits through the plurality of word lines, wherein a slit of the plurality of slits separates the plurality of word lines into a first word line region and a second word line region, and wherein forming the recess along the edge of the first word line plate includes forming the recess along the slit.

15. The method of claim 10 , wherein the second material filling the recess along the edge of the first word line plate is also disposed along an edge of the slit.

16. A computing device, comprising:

one or more processors; and

a memory array coupled to the one or more processors, wherein the memory array includes:

a plurality of word lines, wherein a word line includes a first word line plate and a second word line plate that are co-planar with one another and separated from one another by a slit such that the first word line plate is not directly physically coupled with the second word line plate, wherein the first word line plate has a substantially rectangular shape that extends in an X direction, wherein the first word line plate includes a first material with a first resistivity, wherein an edge of the first word line plate is recessed and filled with a second material that has a second resistivity that is lower than the first resistivity to reduce total resistance of the word line, wherein the first material is in direct physical contact with the second material, and wherein the slit is filled with an insulating material that is in direct contact with the second material; and

wherein the memory array further includes a plurality of pillars disposed to intersect with the plurality of word lines in a Y direction that is orthogonal to the X direction in which the first word line plate forms the substantially rectangular shape, wherein a pillar of the plurality of pillars is in direct physical contact with the first material at an intersection of the pillar with the first word line plate.

17. The computing device of claim 16 , wherein the memory array is a three dimensional double density flash memory.

18. The computing device of claim 16 , wherein the first material includes polysilicon, and the second material includes a metal; and wherein the pillar of the plurality of pillars includes a number of storage cells, wherein a storage cell includes a channel trapping layer surrounded by the word line, and a cell channel region surrounded by the channel trapping layer.

19. The computing device of claim 18 , wherein storage cells within the first word line plate form a first memory block, and storage cells within the second word line plate form a second memory block.