Contact integration for three-dimensional stacking semiconductor devices
View Patent ↗Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.
1. A method, comprising:
forming a first active layer;
depositing an intermediate layer on the first active layer;
providing an upper layer on and directly adjacent to the intermediate layer without forming an interconnect between the first active layer and the upper layer;
forming an opening through the upper layer and the intermediate layer to expose a contact feature of the first active layer, wherein the upper layer is devoid of active devices; and
forming a contact in the opening, wherein the contact is formed on and directly adjacent to the contact feature in the first active layer and wherein the contact substantially fills the opening to a top surface of the upper layer;
wherein the opening is formed using a full-pitch lithography process and the contact feature is formed using a half-pitch or smaller lithography process.
2. The method of claim 1 , wherein the intermediate layer is a dielectric layer formed on the first active layer and wherein the first active layer comprises a dielectric top surface.
3. The method of claim 1 , further comprising planarizing the first active layer prior to depositing the intermediate layer.
4. The method of claim 3 , wherein the upper layer is formed on the intermediate layer using a wafer bonding process.
5. The method of claim 1 , further comprising planarizing the upper layer.
6. The method of claim 1 , further comprising forming active devices on the upper layer to form a second active layer, wherein the active devices comprise portions of the upper layer.
7. The method of claim 1 , wherein the contact feature is one or more of a source, a drain, a gate, or a wordline.
8. An integrated circuit comprising a self-aligned contact to connect a contact feature in a first active layer to a second active layer, wherein the self-aligned contact is formed by:
depositing an intermediate layer over the first active layer, providing an upper layer on and directly adjacent to the intermediate layer without forming an interconnect between the first active layer and the upper layer, forming an opening through the upper layer and the intermediate layer to expose the contact feature in the first active layer wherein the upper layer is devoid of active devices, and forming the self-aligned contact in the opening;
wherein the opening is formed using a full-pitch lithography process and the contact feature is formed using a half-pitch or smaller lithography process.
9. The integrated circuit of claim 8 , wherein the integrated circuit is a dual-deck NAND memory array.
10. The integrated circuit of claim 9 , wherein the contact connects the bitline to a plurality of memory strings.
11. The integrated circuit of claim 10 , further comprising a third active layer on the second active layer and wherein the bitline in the first active layer is connected to the third active layer.
12. The integrated circuit of claim 8 , wherein the upper layer is formed using a wafer bonding process.