Charge pump warm-up current reduction
View Patent ↗A charge pump circuit includes a voltage controlled oscillator. The voltage controlled oscillator operates at a lower frequency during a warm-up mode, and operates at a higher frequency during a loading mode. The lower frequency operation during the warm-up mode reduces power supply current requirements.
1. A charge pump comprising:
a voltage controlled oscillator (VCO) to produce a clock signal having a variable frequency in response to an error signal;
a pump stage to produce an output voltage in response to the clock signal;
a differential amplifier to produce the error signal in response to the output voltage and a reference voltage; and
a bias circuit to bias the VCO by modifying a DC voltage component of the error signal, the bias circuit capable of commanding a lower nonzero VCO output frequency during a warm-up mode and a higher nonzero VCO frequency during a loading mode, wherein the bias circuit includes at least one diode-connected transistor to modify the DC voltage component of the error signal, the bias circuit further includes two diode-connected transistors and two switches to conditionally couple the two diode-connected transistors to an output node of the differential amplifier, and wherein the two switches are closed during the warm-up mode, and only one of the switches is closed during the loading mode.
2. The charge pump of claim 1 wherein the differential amplifier comprises an output stage with an NMOS load device.
3. The charge pump of claim 2 wherein the two diode-connected transistors and two switches form a plurality of current paths to modify a DC current through the NMOS load device.
4. A method comprising:
starting a charge pump circuit with a first nonzero internal clock frequency during a warm-up mode by biasing an error signal fed from an output node of an error amplifier to a voltage controlled oscillator (VCO) with a first DC voltage by closing two switches coupled to the output node of the error amplifier; and
operating the charge pump circuit with a second nonzero internal clock frequency during a loading mode by biasing the error signal fed to the VCO with a second DC voltage by closing one of the two switches coupled to the output of the error amplifier.
5. The method of claim 4 wherein the first nonzero internal clock frequency is lower than the second nonzero internal clock frequency.
6. The method of claim 4 further comprising supplying a charge pump output voltage to a circuit within a flash memory device.