Gate structures for flash memory and methods of making same
View Patent ↗A process may include forming a polysilicon pinnacle above and on a polysilicon island and further forming a floating gate from the polysilicon pinnacle and polysilicon island. The floating gate can bear an inverted T-shape. The floating gate can also be disposed above an isolated semiconductive substrate such as in a shallow-trench isolation semiconductive substrate. Electronic devices may include the floating gate as part of a field effect transistor.
1. A process comprising:
forming a spacer first mask above a substrate;
etching through an antireflective coating (ARC) layer and a carbon layer using the spacer first mask to form a spacer second mask that includes a portion of the ARC layer disposed upon a portion of the carbon layer;
etching through a nitride layer using the spacer second mask to form a first pillar that includes a portion of the carbon layer disposed upon the nitride layer;
forming a spacer third mask that includes the first pillar disposed upon a polycrystalline silicon layer;
forming a second pillar using the spacer third mask, wherein the second pillar includes a portion of the nitride layer disposed upon a portion of a polycrystalline silicon layer, a portion of the polycrystalline silicon being disposed upon a gate oxide layer, the gate oxide layer disposed upon a semiconductive substrate, and wherein the semiconductive substrate includes a trench; and
forming a floating gate by removing the portion of the nitride layer and filling a pinnacle polysilicon to contact a portion of the polycrystalline silicon layer.
2. The process of claim 1 , further including:
forming a gate select oxide above the floating gate; and
forming a gate select above the floating gate and above and on the gate select oxide.
3. The process of claim 1 , wherein forming the spacer first mask includes:
patterning a resist upon the ARC;
forming a first dielectric film over the resist; and
spacer etching the first dielectric film to form the spacer first mask.
4. The process of claim 1 , wherein forming the spacer third mask includes:
forming a second dielectric film over the first pillar; and
spacer etching the second dielectric film.
5. The process of claim 4 , wherein forming the polysilicon pinnacle includes:
forming the second pillar;
removing the second dielectric film;
filling a bulk dielectric over the portion of the nitride layer;
removing the portion of the nitride layer to form a recess; and
filling polysilicon into the recess.
6. The process of claim 1 , wherein forming the first pillar includes etching the nitride layer in the presence of at least one fluorocarbon compound.
7. The process of claim 1 , wherein forming the second pillar includes etching the polysilicon layer in the presence of a halogen compound.
8. The process of claim 1 , wherein filling a pinnacle polysilicon to contact a portion of the polycrystalline polysilicon includes depositing polysilicon into a geometry in a range from about 18 nm to about 22 nm, followed by etching back excess polysilicon.
9. A process comprising:
forming a spacer first mask above a substrate;
etching through an antireflective coating (ARC) layer and a carbon layer using the spacer first mask to form a spacer second mask that includes a portion of the ARC layer disposed upon a portion of the carbon layer;
etching through a nitride layer using the spacer second mask to form a first pillar that includes a portion of the carbon layer disposed upon the nitride layer;
forming a spacer third mask that includes the first pillar disposed upon a semiconductive layer;
forming a second pillar using the spacer third mask, wherein the second pillar includes a portion of the nitride layer disposed upon a portion of the semiconductive layer, a portion of the semiconductive layer being disposed upon a gate dielectric layer, the gate dielectric layer disposed upon a semiconductive substrate, and wherein the semiconductive substrate includes a trench;
forming a floating gate by removing the portion of the nitride layer and filling a semiconductive pinnacle to contact a portion of the semiconductive layer;
forming a gate select dielectric above the floating gate; and
forming a gate select above the floating gate and above and on the gate select dielectric.
10. The process of claim 9 , wherein forming the spacer first mask includes:
patterning a resist upon the ARC;
forming a first dielectric film over the resist; and
spacer etching the first dielectric film to form the spacer first mask.
11. The process of claim 9 , wherein forming the spacer third mask includes:
forming a second dielectric film over the first pillar; and
spacer etching the second dielectric film.
12. The process of claim 11 , wherein forming the semiconductive pinnacle includes:
forming the second pillar;
removing the second dielectric film;
filling a bulk dielectric over the portion of the nitride layer;
removing the portion of the nitride layer to form a recess; and
filling a semiconductive material into the recess.
13. The process of claim 9 , wherein forming the first pillar includes etching the nitride layer in the presence of at least one fluorocarbon compound.
14. The process of claim 9 , wherein forming the second pillar includes etching the semiconductive layer in the presence of a halogen compound.
15. The process of claim 9 , wherein filling a semiconductive pinnacle to contact a portion of the semiconductor includes depositing a semiconductor into a geometry in a range from about 18 nm to about 22 nm, followed by etching back excess semiconductor.