Maximum-likelihood decoder in a memory controller for synchronization

1. A method comprising:

receiving a constrained codeword from a non-volatile memory (NVM) via a channel, wherein the NVM is a multi-level cell memory in which cells that store different bit combinations are accessible with different voltage levels and wherein data content of the NVM is organized into pages of information where bits of a same bit combination map to a different page, the constrained codeword including an appended bit-stream; and

decoding the received constrained codeword with the use of voltage level information for some but not all of the pages by reconstructing the appended bit-stream and invoking a synchronization procedure that applies a maximum-likelihood (ML) estimator to estimate locations of any insertion, deletion, or error in the reconstructed appended bit-stream.

2. The method of claim 1 , wherein the appended bit stream is generated by inserting bits that indicate which of a special pattern, from among special patterns, occurred in an input.

3. The method of claim 2 , wherein the appended bit-stream is further generated by:

appending a one-bit to the appended bit-stream when the special pattern is mapped to another pattern; and

appending a zero-bit to the appended bit-stream when the special pattern remains unchanged.

4. The method of claim 2 , wherein decoding comprises:

comparing the reconstructed appended bit-stream with a noisy appended bit-stream which includes errors and insertions or deletions, the comparing to determine any mismatch between the reconstructed appended bit-stream and the noisy appended bit-stream,

wherein the synchronization procedure is invoked when a mismatch is determined.

5. The method of claim 2 , wherein the special patterns for a 3-bit multi-level-cell (MLC) include:

a 7-0-7 level pattern;

a 6-0-7 level pattern;

a 7-0-6 level pattern;

a 6-1-6 level pattern;

a 6-1-7 level pattern; and

a 7-1-6 level pattern.

6. The method of claim 1 , wherein the synchronization procedure comprises:

generating a Trellis to determine a location and pattern of a most likely insertion or deletion in the reconstructed appended bit-stream, the Trellis having states with associated deletion and insertion probabilities; and

mapping a pattern, in the reconstructed appended bit-stream, at the most likely location with the most likely insertion or deletion determined by the Trellis.

7. The method of claim 6 , wherein the synchronization procedure comprises:

computing the deletion probabilities in the reconstructed appended bit-stream; and

computing the insertion probabilities in the reconstructed appended bit-stream.

8. The method of claim 6 further comprises:

appending a predetermined bit pattern, at the end of the appended bit-stream, to terminate the Trellis.

9. The method of claim 8 , wherein the predetermined bit pattern is a non-zero bit pattern.

10. The method of claim 1 , wherein the ML estimator is a truncated Viterbi detector to estimate whether an insertion, deletion, or an error occurred in the reconstructed appended bit-stream.

11. The method of claim 1 further comprises:

initializing the appended bit-stream to a null stream.

12. The method of claim 1 , wherein the NVM is a NAND flash memory.

13. The method of claim 1 , wherein the appended bit-stream is a variable length bit-stream.

14. A memory controller comprising:

a decoder circuit to:

receive a constrained codeword from a non-volatile memory (NVM) via a channel, wherein the NVM is a multi-level cell memory in which cells that store different bit combinations are accessible with different voltage levels and wherein data content of the NVM is organized into pages of information where bits of a same bit combination map to a different page, the constrained codeword including an appended bit-stream; and

decode the received constrained codeword with the use of voltage level information for some but not all of the pages by reconstructing the appended bit-stream and invoking a synchronization procedure that applies a maximum-likelihood (ML) estimator to estimate locations of any insertion, deletion, or error in the reconstructed appended bit-stream.

15. The memory controller of claim 14 further comprising:

an encoder circuit to:

generate the appended bit stream by inserting bits that indicate which of a special pattern, from among special patterns, occurred in an input;

append a one-bit to the appended bit-stream when the special pattern is mapped to another pattern; and

append a zero-bit to the appended bit-stream when the special pattern remains is unchanged.

16. The memory controller of claim 15 , wherein the encoder circuit is operable to:

append a predetermined bit pattern, at the end of the appended bit-stream, to terminate the Trellis.

17. The memory controller of claim 16 , wherein the predetermined bit pattern is a non-zero bit pattern.

18. The memory controller of claim 15 , wherein the encoder is to:

initialize the appended bit-stream to a null stream.

19. The memory controller of claim 14 , wherein the decoder circuit is operable to:

compare the reconstructed appended bit-stream with a noisy appended bit-stream which includes errors and insertions or deletions, the comparison to determine any mismatch between the reconstructed appended bit-stream and the noisy appended bit-stream,

wherein the synchronization procedure is invoked when a mismatch is determined.

20. The memory controller of claim 14 , wherein the decoder circuit is operable to perform the synchronization procedure by:

generating a Trellis to determine a location and pattern of a most likely insertion or deletion in the reconstructed appended bit-stream, the Trellis having states with associated deletion and insertion probabilities; and

mapping a pattern, in the reconstructed appended bit-stream, at the most likely location with the most likely insertion or deletion determined by the Trellis.

21. The memory controller of claim 20 , wherein the decoder circuit is further operable to:

compute the deletion probabilities in the reconstructed appended bit-stream; and

compute the insertion probabilities in the reconstructed appended bit-stream.

22. The memory controller of claim 14 , wherein the ML estimator is a truncated Viterbi detector to estimate whether an insertion, deletion, or an error occurred in the reconstructed appended bit-stream.

23. The memory controller of claim 14 , wherein the NVM is a NAND flash memory.

24. A system comprising:

one or more processors coupled to a memory controller, the memory controller coupled to a non-volatile memory (NVM) via a channel, wherein the NVM is a multi-level cell memory in which cells that store different bit combinations are accessible with different voltage levels and wherein data content of the NVM is organized into pages of information where bits of a same bit combination map to a different page, the memory controller comprises:

a decoder circuit to:

receive a constrained codeword from the NVM via the channel, the constrained codeword including an appended bit-stream; and

decode the received constrained codeword with the use of voltage level information for some but not all of the pages by reconstructing the appended bit-stream and invoking a synchronization procedure that applies a maximum-likelihood (ML) estimator to estimate locations of any insertion, deletion, or error in the reconstructed appended bit-stream; and

a display unit to display stored content.

25. The system of claim 24 further comprises:

an encoder circuit to:

generate the appended bit stream by inserting bits that indicate which of a special pattern, from among special patterns, occurred in an input;

append a one-bit to the appended bit-stream when the special pattern is mapped to another pattern; and

append a zero-bit to the appended bit-stream when the special pattern remains is unchanged.

26. The system of claim 25 , wherein the encoder circuit is operable to:

append a predetermined bit pattern, at the end of the appended bit-stream, to terminate the Trellis.

27. The system of claim 24 , wherein the decoder circuit is operable to:

compare the reconstructed appended bit-stream with a noisy appended bit-stream which includes errors and insertions or deletions, the comparing to determine any mismatch between the reconstructed appended bit-stream and the noisy appended bit-stream,

wherein the synchronization procedure is invoked when a mismatch is determined.

28. The system of claim 24 , wherein the decoder circuit is operable to perform the synchronization procedure by:

generating a Trellis to determine a location and pattern of a most likely insertion or deletion in the reconstructed appended bit-stream, the Trellis having states with associated deletion and insertion probabilities; and

mapping a pattern, in the reconstructed appended bit-stream, at the most likely location with the most likely insertion or deletion determined by the Trellis.

29. The system of claim 24 , wherein the NVM is a NAND flash memory.

30. An article of manufacture having a machine storage medium containing machine executable instructions that when executed cause a processor to perform a method, the method comprising:

receiving a constrained codeword from a non-volatile memory (NVM) via a channel, wherein the NVM is a multi-level cell memory in which cells that store different bit combinations are accessible with different voltage levels and wherein data content of the NVM is organized into pages of information where bits of a same bit combination map to a different page, the constrained codeword including an appended bit-stream; and

decoding the received constrained codeword with the use of voltage level information for some but not all of the pages by reconstructing the appended bit-stream and invoking a synchronization procedure that applies a maximum-likelihood (ML) estimator to estimate locations of any insertion, deletion, or error in the reconstructed appended bit-stream.