Program suspend-resume techniques in non-volatile storage
In one example, a nonvolatile memory device, such as a NAND flash memory device, includes an array of non-volatile memory cells. Program operations performed by the memory may be suspended (e.g., in order to service a high priority read request). The memory device includes a timer to track a duration of time the program operation is suspended. Upon program resume, the controller applies a program voltage after resume that is adjusted based on the duration of time the program operation is suspended.
1. A non-volatile memory device comprising:
an array of non-volatile memory cells;
control circuitry to suspend a program operation to program cells of the array; and
a timer to track a duration of time the program operation is suspended;
the control circuitry to resume the program operation with a next program voltage based on the duration of time the program operation is suspended.
2. The non-volatile memory device of claim 1 , wherein:
the timer is to start to track the duration in response to receipt of a signal indicating a program suspend; and
the timer is to stop to track the duration in response to receipt of a signal indicating a program resume.
3. The non-volatile memory device of claim 1 , wherein:
the control circuitry is to determine the next program voltage based further on a pre-suspend program voltage.
4. The non-volatile memory device of claim 3 , wherein:
the control circuitry is to determine the next program voltage based on the pre-suspend program voltage minus a voltage based on the duration of time the program operation is suspended.
5. The non-volatile memory device of claim 3 , wherein:
the control circuitry is to determine the next program voltage as: the pre-suspend program voltage plus a voltage step based on cell state minus a voltage based on the duration of time the program operation is suspended.
6. The non-volatile memory device of claim 1 , wherein:
the non-volatile memory device comprises a solid state drive (SSD).
7. The non-volatile memory device of claim 1 , wherein the array comprises a NAND flash memory array.
8. The non-volatile memory device of claim 1 , wherein the control circuitry and the array of non-volatile memory cells communicate over an Open NAND Flash Interface (ONFI) interface.
9. An apparatus, comprising:
a host comprising a processor and a solid state drive (SSD) interface; and
a solid state drive (SSD) coupled with the host via the SSD interface of the host, the solid state drive including:
an array of non-volatile memory cells;
control circuitry to suspend a program operation to program cells of the array; and
a timer to track a duration of time the program operation is suspended;
the control circuitry to resume the program operation with a next program voltage based on the duration of time the program operation is suspended.
10. The apparatus of claim 9 , wherein:
the timer is to start to track the duration in response to receipt of a signal indicating a program suspend; and
the timer is to stop to track the duration in response to receipt of a signal indicating a program resume.
11. The apparatus of claim 9 , wherein:
the control circuitry is to determine the next program voltage based further on a pre-suspend program voltage.
12. The apparatus of claim 11 , wherein:
the control circuitry is to determine the next program voltage based on the pre-suspend program voltage minus a voltage based on the duration of time the program operation is suspended.
13. The apparatus of claim 11 , wherein:
the control circuitry is to determine the next program voltage as: the pre-suspend program voltage plus a voltage step based on cell state minus a voltage based on the duration of time the program operation is suspended.
14. The apparatus of claim 9 , wherein the array comprises a NAND flash memory array.
15. The apparatus of claim 9 , wherein the control circuitry and the array of non-volatile memory cells communicate over an Open NAND Flash Interface (ONFI) interface.
16. The apparatus of claim 9 , wherein the SSD interface comprises a Non-Volatile Memory Express (NVMe) interface.
17. An article of manufacture comprising a computer readable storage medium having content stored thereon which when accessed causes one or more processors to execute operations to perform a method comprising:
sending, from control circuitry of an SSD, a suspend command to a nonvolatile memory to suspend a program operation;
starting a timer circuit in response to the suspend command;
sending a resume command to the nonvolatile memory;
stopping the timer circuit in response to the resume command;
determining a time between the suspend command and resume command; and
resuming the program operation with a program voltage adjusted based on the time.
18. The article of manufacture of claim 17 , the method further comprising:
determining the program voltage based further on a pre-suspend program voltage.
19. The article of manufacture of claim 18 , the method further comprising:
determining the program voltage based on the pre-suspend program voltage minus a voltage based on a duration of the time.
20. The article of manufacture of claim 19 , the method further comprising:
determining the pre-suspend program voltage based on a verify operation after the resume command.