Program verify technique for non-volatile memory
A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.
1. A non-volatile storage device comprising:
a storage array including strings of memory cells;
logic to:
apply a voltage to wordlines of a string to perform a program verify;
ramp down the voltage applied to two or more of the wordlines between a selected wordline and at least one end of the string one at a time; and
a register to store a value to indicate a time delay between ramping down wordlines one at a time.
2. The non-volatile storage device of claim 1 , wherein:
the at least one end of the string includes a source or drain of the string.
3. The non-volatile storage device of claim 1 , wherein:
the storage array comprises a 3D NAND array;
the string comprises a 3D NAND string; and
the at least one end of the string includes a select gate source (SGS) or a select gate drain (SGD).
4. The non-volatile storage device of claim 1 , wherein:
the two or more wordlines to be ramped down one at a time include wordlines neighboring the selected wordline.
5. The non-volatile storage device of claim 1 , wherein the logic to ramp down the voltage is to:
ramp down the voltage applied to the two or more wordlines one at a time and sequentially in a direction from at least one end of the string to the selected wordline.
6. The non-volatile storage device of claim 1 , wherein the logic is to:
after ramp down of the voltage applied to the two or more wordlines, ramp down the voltage applied to two or more of remaining wordlines on the string one at a time and sequentially from the selected wordline towards the other end of the string.
7. The non-volatile storage device of claim 1 , wherein the logic is to:
after ramp down of the voltage applied to the two or more wordlines, ramp down the voltage applied to remaining wordlines on the string at the same time.
8. The non-volatile storage device of claim 1 , wherein the logic to ramp down the voltage is to:
ramp down the voltage applied to the two or more wordlines one at a time and sequentially in a direction from source to drain of the string.
9. The non-volatile storage device of claim 1 , wherein the logic to ramp down the voltage is to:
ramp down the voltage applied to the two or more wordlines one at a time and sequentially in a direction from drain to source of the string.
10. The non-volatile storage device of claim 1 , wherein:
the non-volatile storage device comprises a solid state drive (SSD).
11. A three-dimensional (3D) NAND die comprising:
a 3D NAND array including NAND strings of memory cells;
logic to:
apply a voltage to wordlines of a string to perform a program verify;
ramp down the voltage applied to two or more of the wordlines between a selected wordline and at least one end of the string one at a time; and
a register to store a value to indicate a number of wordlines to be ramped down one at a time.
12. The 3D NAND die of claim 11 , wherein:
the two or more wordlines to be ramped down one at a time include wordlines neighboring the selected wordline.
13. The 3D NAND die of claim 11 , wherein:
ends of the string include a select gate source (SGS) and a select gate drain (SGD).
14. The 3D NAND die of claim 11 , wherein the logic to ramp down the voltage is to:
ramp down the voltage applied to the two or more wordlines one at a time and sequentially in a direction from at least one end of the string to the selected wordline.
15. The 3D NAND die of claim 11 , wherein the logic is to:
after ramp down of the voltage applied to the two or more wordlines, ramp down the voltage applied to two or more of remaining wordlines on the string one at a time and sequentially from the selected wordline towards the other end of the string.
16. The 3D NAND die of claim 11 , wherein the logic is to:
after ramp down of the voltage applied to the two or more wordlines, ramp down the voltage applied to remaining wordlines on the string at the same time.
17. A system comprising:
a non-volatile storage device comprising:
a storage array including strings of memory cells;
logic to:
apply a voltage to wordlines of a string to perform a program verify; and
ramp down the voltage applied to two or more wordlines between a selected wordline and at least one end of the string one at a time; and
a register to store a value to indicate a time delay between ramping down wordlines one at a time; and
a processor coupled with the non-volatile storage device.
18. The system of claim 17 , wherein:
the storage array comprises a 3D NAND array;
the string comprises a 3D NAND string; and
the at least one end of the string includes a select gate source (SGS) or a select gate drain (SGD).
19. The system of claim 17 , wherein:
the two or more wordlines to be ramped down one at a time include wordlines neighboring the selected wordline.
20. The system of claim 17 , wherein the logic to ramp down the voltage is to:
ramp down the voltage applied to the two or more wordlines one at a time and sequentially in a direction from at least one end of the string to the selected wordline.