Write process for a non volatile memory device

1. An apparatus, comprising:

a non volatile memory device comprising a controller to implement a coarse write process for the non volatile memory device, the non volatile memory device comprising storage cells to store more than two logic states, wherein, the coarse write process is to perform a verify operation after an initial charge pulse to identify less responsive storage cells and transfer additional charge to the less responsive storage cells as compared to non less responsive storage cells that are to be programmed to a same logical state as the less responsive storage cells without performing a following verify operation after each pulse of charge applied during the coarse write process.

2. The apparatus of claim 1 wherein the coarse write process is to apply one additional charge transfer to the less responsive storage cells than the non less responsive cells.

3. The apparatus of claim 2 wherein the one additional charge transfer is also used to program other ones of the storage cells that are being programmed to a higher voltage logical state than the logical state that the less responsive storage cells are being programmed to.

4. The apparatus of claim 1 wherein the coarse write process further comprises a number of charge transfers that is equal to a number of different logical states being programmed.

5. The apparatus of claim 1 where the additional charge produces a narrowed charge distribution for the logical state to which the less responsive storage cells are being programmed, the narrowed charge distribution characterized by an eliminated lower tail.

6. The apparatus of claim 1 wherein the verify operation is performed and the additional charge is provided during a coarse phase of a write process that precedes a fine phase of the write process.

7. The apparatus of claim 1 wherein the non volatile memory device is a FLASH device.

8. A computing system, comprising: a display;

a plurality of processing cores;

a main memory;

a main memory controller coupled between the plurality of processing cores and the main memory; and,

a non volatile memory device comprising a controller to implement a coarse write process for the non volatile memory device, the non volatile memory device comprising storage cells to store more than two logic states, wherein, the coarse write process is to perform a verify operation after an initial charge pulse to identify less responsive storage cells and transfer additional charge to the less responsive storage cells as compared to non less responsive storage cells that are to be programmed to a same logical state as the less responsive storage cells without performing a following verify operation after each pulse of charge applied during the coarse write process.

9. The computing system of claim 8 wherein the coarse write process is to apply one additional charge transfer to the less responsive storage cells than the non less responsive cells.

10. The computing system of claim 9 wherein the one additional charge transfer is also used to program other ones of the storage cells that are being programmed to a higher voltage logical state than the logical state that the less responsive storage cells are being programmed to.

11. The computing system of claim 8 wherein the coarse write process further comprises a number of charge transfers that is equal to a number of different logical states being programmed.

12. The computing system of claim 8 where the additional charge produces a narrowed charge distribution for the logical state to which the less responsive storage cells are being programmed, the narrowed charge distribution characterized by an eliminated lower tail.

13. The computing system of claim 8 wherein the verify operation is performed and the additional charge is provided during a coarse phase of a write process that precedes a fine phase of the write process.

14. The computing system of claim 13 wherein the coarse phase is followed by a fine phase of the write process.

15. A machine readable storage medium containing program code that when processed by a processor of a non volatile storage device causes a coarse write method to be performed, the non volatile storage device comprising storage cells that are able to store more than two logic states, the coarse write method comprising:

performing a verify operation after an initial charge pulse to identify less responsive storage cells; and,

transferring additional charge to the less responsive storage cells as compared to non less responsive storage cells that are being programmed to a same logical state as the less responsive storage cells without performing a following verify operation after each pulse of charge applied during the coarse write method.

16. The machine readable storage medium of claim 15 wherein the course write method is to apply one additional charge transfer to the less responsive storage cells than the non less responsive cells.

17. The machine readable storage medium of claim 16 wherein the one additional charge transfer is also used to program other ones of the storage cells that are being programmed to a higher voltage logical state than the logical state that the less responsive storage cells are being programmed to.

18. The machine readable storage medium of claim 15 wherein the coarse write method further comprises a number of charge transfers that is equal to a number of different logical states being programmed.

19. The machine readable storage medium of claim 15 where the additional charge produces a narrowed charge distribution for the logical state to which the less responsive storage cells are being programmed, the narrowed charge distribution characterized by an eliminated lower tail.

20. The machine readable storage medium of claim 15 wherein the verify operation is performed and the additional charge is provided during a coarse phase of a write method that precedes a fine phase of the coarse write method.