Vertical memory device and method
View Patent ↗Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate. The horizontal member of the first gate overlaps the horizontal member of the second gate.
1. A method of making a memory cell, comprising:
forming a body on a substrate, said body extending vertically from said substrate;
forming a first gate comprising a vertical member and a horizontal member, wherein said first gate is disposed laterally from said body; and
forming a second gate comprising a vertical member and a horizontal member, wherein said second gate is disposed laterally from said first gate;
wherein said horizontal member of said first gate overlaps said horizontal member of said second gate.
2. The method of claim 1 , further comprising forming a spacer layer having a width around said first gate, wherein said width determines a horizontal extension of said horizontal member of said first gate.
3. The method of claim 1 , further comprising forming a first dielectric layer between said first gate and said body.
4. The method of claim 3 , wherein forming said first dielectric comprises forming a vertical portion having a first thickness adjacent to said body and forming a horizontal portion having a second thickness adjacent to said substrate, wherein said second thickness is greater than said first thickness.
5. The method of claim 4 , wherein forming said first dielectric comprises forming said first dielectric using a dopant enhanced oxidation process.
6. The method of claim 4 , wherein forming said first dielectric comprises forming said first dielectric using a directional dielectric deposition process.
7. The method of claim 1 , further comprising forming a second dielectric between said first and second gates.
8. The method of claim 7 , wherein forming said second dielectric comprises forming an oxide-nitride-oxide.
9. The method of claim 1 , further comprising forming a horizontal overlapping region of said first and second gates wherein a capacitive coupling ratio between said first and second gates is between 0.3 and 0.6.