Programming memory devices
Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can perform a first programming pass to program a memory cell in the plurality of memory cells. A defined number of blanket programming pulses can be applied to the memory cell during the first programming pass. The blanket programming pulses may not include verify operations. The memory controller can perform a second programming pass to program the memory cell. A defined number of program and verify (PV) pulses can be applied to the memory cell during the second programming pass.
1. A memory device operable to program memory cells in the memory device, the memory device comprising:
a plurality of memory cells; and
a memory controller comprising logic to:
perform a prologue programming pass prior to a first programming pass to achieve a stationary programming condition for a memory cell in the plurality of memory cells and set an initial state for the first programming pulse, wherein the prologue programming pass includes applying a defined number of incremental program and verify (PV) pulses to the memory cell prior to the first programming pass;
perform the first programming pass to program the memory cell in the plurality of memory cells, wherein a defined number of blanket programming pulses are applied to the memory cell during the first programming pass, and the blanket programming pulses do not include verify operations; and
perform a second programming pass to program the memory cell, wherein a defined number of PV pulses are applied to the memory cell during the second programming pass.
2. The memory device of claim 1 , wherein the memory controller comprises further logic to:
perform the first programming pass by applying the defined number of blanket programming pulses to transform a defined number of levels in the memory cell into a defined number of intermediate coarse levels in the memory cell; and
perform the second programming pass by applying the defined number of PV pulses to the defined number of intermediate coarse levels in the memory cell.
3. The memory device of claim 1 , wherein:
the first programming pass includes a defined number of incremental step pulse programming (ISPP) blanket programming pulses without the verify operations; and
the second programming pass includes a defined number of PV ISPP programming pulses.
4. The memory device of claim 1 , wherein the memory controller further comprises logic to perform a two-pass programming procedure that includes the first programming pass and the second programming pass, wherein the first programming pass excludes verify operations and the second programming pass includes verify operations.
5. The memory device of claim 1 , wherein the memory controller further comprises logic to perform the first programming pass without the verify operations to reduce a programming time for programming the memory cell.
6. The memory device of claim 1 , wherein the defined number of blanket programming pulses and the defined number of PV pulses depend on a number of bits in the memory cell.
7. The memory device of claim 1 , wherein the plurality of memory cells are multi-bit cells.
8. The memory device of claim 1 , wherein the plurality of memory cells are quad-level cells (QLC) with 4 bits per cell.
9. The memory device of claim 1 , wherein the memory device is a NAND flash memory device.
10. A NAND flash memory device operable to program memory cellsin the NAND memory device, the NAND memory device comprising:
a plurality of memory cells; and
a memory controller comprising logic to:
perform a prologue programming pass prior to a first programming pass to achieve a stationary programming condition for a memory cell in the plurality of memory cells and set an initial state for the first programming pulse, wherein the prologue programming pass includes applying a defined number of incremental program and verify (PV) pulses to the memory cell prior to the first programming pass;
perform the first programming pass to program a defined number of levels in the memory cell in the plurality of memory cells, wherein a defined number of blanket programming pulses are applied to the defined number of levels in the memory cell during the first programming pass, and the blanket programming pulses do not include verify operations; and
perform a second programming pass to program the defined number of levels in the memory cell after completion of the first programming pass, wherein a defined number of PV pulses are applied to the defined number of levels in the memory cell during the second programming pass.
11. The NAND flash memory device of claim 10 , wherein the memory controller further comprises logic to:
perform the first programming pass in order to transform the defined number of levels in the memory cell into a defined number of intermediate coarse levels in the memory cell; and
perform the second programming pass by applying the defined number of PV pulses to the defined number of intermediate coarse levels in the memory cell.
12. The NAND flash memory device of claim 10 , wherein:
the first programming pass includes a defined number of incremental step pulse programming (ISPP) blanket programming pulses without the verify operations; and
the second programming pass includes a defined number of PV ISPP programmingpulses.
13. The NAND flash memory device of claim 10 , wherein the memory controller further comprises logic to perform a two-pass programming mechanism that includes the first programming pass and the second programming pass, wherein the first programming pass excludes verify operations and the second programming pass includes verify operations.
14. The NAND flash memory device of claim 10 , wherein the memory controller further comprises logic to perform the first programming pass without the verify operations to reduce a programming time for programming the memory cell.
15. The NAND flash memory device of claim 10 , wherein the defined number of levels in the memory cell depends on a number of bits in the memory cell, and the defined number of blanket programming pulses and the defined number of PV pulses correspond to the defined number of levels.
16. The NAND flash memory device of claim 10 , wherein the plurality of memory cells are multi-bit cells.
17. The NAND flash memory device of claim 10 , wherein the plurality of memory cells are quad-level cells (QLC) with 4 bits per cell.
18. A method for programming a memory cell in a memory device, comprising:
performing, at a memory controller in the memory device, a prologue programming pass prior to a first programming pass to achieve a stationary programming condition for the memory cell in the memory device and setting an initial state for the first programming pulse, wherein the prologue programming pass includes applying a defined number of incremental program and verify (PV) pulses to the memory cell prior to the first programming pass;
performing, at the memory controller, the first programming pass to program the memory cell in the memory device, wherein a defined number of blanket programming pulses are applied to the memory cell during the first programming pass, and the blanket programming pulses do not include verify operations; and
performing, at the memory controller, a second programming pass after completion of the first programming pass to program the memory cell, wherein a defined number of PV pulses are applied to the memory cell during the second programming pass.
19. The method of claim 18 , further comprising:
performing the first programming pass by applying the defined number of blanket programming pulses to transform a defined number of levels in the memory cell into a defined number of intermediate coarse levels in the memory cell; and
performing the second programming pass by applying the defined number of PV pulses to the defined number of intermediate coarse levels in the memory cell.
20. The method of claim 18 , further comprising performing a two-pass programming procedure that includes the first programming pass and the second programming pass, wherein the first programming pass excludes verify operations to reduce a programming time and the second programming pass includes verify operations.
21. The method of claim 18 , wherein:
the first programming pass includes a defined number of incremental step pulse programming (ISPP) blanket programming pulses without the verify operations; and the second programming pass includes a defined number of PV ISPP programming pulses.
22. The method of claim 18 , wherein the memory cell is a multi-bit cell.
23. The method of claim 18 , wherein the memory cell is quad-level cell (QLC) with 4 bits of data.
24. The method of claim 18 , wherein the memory device is a NAND flash memory device.