Flash memory devices incorporating a polydielectric layer
View Patent ↗Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.
1. A flash memory device, comprising:
a plurality of insulative layers vertically spaced apart from one another;
a vertically oriented conductive channel extending through the plurality of insulative layers;
a charge storage structure disposed between individual adjacent insulative layers;
a control gate laterally separated from the charge storage structure such that the charge storage structure is between the control gate and the conductive channel; and
at least four dielectric layers disposed between the control gate and the charge storage structure.
2. The flash memory device of claim 1 , wherein a layer of the at least four dielectric layers is adjacent to the charge storage structure and comprises a nitride material.
3. The flash memory device of claim 2 , wherein the nitride material comprises silicon nitride.
4. The flash memory device of claim 1 , wherein a layer of the at least four dielectric layers is adjacent to the charge storage structure and comprises an oxide material.
5. The flash memory device of claim 4 , wherein the oxide material comprises aluminum oxide.
6. The flash memory device of claim 1 , wherein a layer of the at least four dielectric layers is adjacent to the charge storage structure and comprises a high dielectric constant material.
7. The flash memory device of claim 6 , wherein the high dielectric constant material comprises HfOx, HfAlOx, or a combination thereof.
8. The flash memory device of claim 1 , wherein a layer of the at least four dielectric layers is adjacent to at least portions of three sides of the charge storage structure.
9. The flash memory device of claim 1 , wherein the at least four dielectric layers comprises alternating layers of oxide material and nitride material.
10. The flash memory device of claim 9 , wherein the oxide material comprises silicon oxide.
11. The flash memory device of claim 9 , wherein the nitride material comprises silicon nitride.
12. The flash memory device of claim 1 , wherein a layer of the at least four dielectric layers is adjacent to the charge storage structure and has a thickness of from about 1 nm to about 5 nm.
13. The flash memory device of claim 1 , wherein a first layer of the at least four dielectric layers is adjacent to the charge storage structure, and a ratio of a thickness of the first layer to a thickness of a second layer of the at least four dielectric layers is from about 1:2 to about 1:5.
14. The flash memory device of claim 13 , wherein the second layer is adjacent to the first layer.
15. The flash memory device of claim 1 , wherein the at least four dielectric layers are configured to provide a program-erase window that is sufficient for operation of a quad level cell (QLC).
16. The flash memory device of claim 1 , wherein the at least four dielectric layers are configured to provide a band gap that is sufficient for operation of a quad level cell (QLC).
17. The flash memory device of claim 1 , wherein the charge storage structure is a floating gate or a charge trap.
18. The flash memory device of claim 1 , further comprising a tunnel dielectric layer disposed between the charge storage structure and the conductive channel.
19. The flash memory device of claim 1 , wherein the plurality of insulative layers comprises an oxide material, an oxynitride material, a nitride material, or a combination thereof.
20. The flash memory device of claim 1 , wherein the conductive channel comprises a polysilicon material, Ge, SiGe, SiC, or a combination thereof.