Self-aligned floating gate in a vertical memory structure
Methods for building a memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate.
1. A method of manufacturing a memory device comprising:
creating a stackup of at least three tier insulating layers alternating with at least two circuit layers, the circuit layers individually include a conductive layer sandwiched between sacrificial layers that are differentiated from the tier insulating layer to allow selective etching of the sacrificial layers without etching the tier insulating layers, creating the stackup to also include modifying the sacrificial layers during deposition to differentiate the sacrificial layers from the tier insulating layers, the sacrificial layers and the tier insulating layers both include silicon oxide, wherein modifying the sacrificial layers during deposition to differentiate includes changing a deposition precursor for the sacrificial layers, changing a film power for the sacrificial layers, changing a pressure for the sacrificial layers or changing a doping for the sacrificial layers;
creating a hole through the stackup;
etching the conductive layers back from the hole;
etching the sacrificial layers back from the hole;
forming a blocking dielectric film inside at least a portion of the hole, the blocking dielectric film no thicker than an individual sacrificial layer of the sacrificial layers;
creating floating gates in the cavities created by the etching of the conductive layers and the sacrificial layers, the floating gates separated from the conductive layers and the tier insulating layers by the blocking dielectric film;
forming a tunneling dielectric film inside the hole; and
filling the hole with semiconductor material, the semiconductor material separated from the floating gates by the tunneling dielectric film.
2. The method of claim 1 , the conductive layers, the floating gates and the semiconductor material comprise polysilicon, and the tier insulating layers and the sacrificial layers comprise an oxide.
3. The method of claim 1 , further comprising:
creating an outer oxide film on an exposed area of the conductive layers after the etching of the conductive layers;
the blocking dielectric film includes a high dielectric film and an inner oxide film, the high dielectric film having a higher dielectric constant than the inner and outer oxide films; and
the conductive layers separated from the floating gates by an inter-poly dielectric includes the high dielectric film sandwiched between the outer oxide film and the inner oxide film.
4. The method of claim 3 , the inner and outer oxide film comprise silicon oxide, and the high dielectric film comprises silicon nitride, aluminum oxide, hafnium oxide, or hafnium silicate.
5. The method of claim 3 , the high dielectric film comprising a nitride.
6. The method of claim 5 , comprising the high dielectric film sandwiched between the outer oxide film and the inner oxide film forming respective oxide-nitride-oxide (ONO) inter-poly dielectrics (IPDs) to separate respective control gates formed in respective conductive layers from respective floating gates.
7. The method of claim 6 , comprising respective control gates are no thicker than respective floating gates and the respective control gates are self-aligned with the respective floating gates.
8. The method of claim 1 , creating the stackup comprises use of different materials for the sacrificial layers and for the tier insulating layers to differentiate the sacrificial layers from the tier insulating layers.
9. A method of manufacturing a memory device comprising:
creating a stackup of at least three tier insulating layers alternating with at least two circuit layers, the circuit layers individually include a conductive layer sandwiched between sacrificial layers that are differentiated from the tier insulating layer to allow selective etching of the sacrificial layers without etching the tier insulating layers, creating the stackup to also include modifying the sacrificial layers after deposition to differentiate the sacrificial layers from the tier insulating layers, the sacrificial layers and the tier insulating layers both include silicon oxide, wherein modifying the sacrificial layers after deposition to differentiate includes plasma processing of the sacrificial layers, thermal annealing of the sacrificial layers, doping of the sacrificial layers or implantation of the sacrificial layers;
creating a hole through the stackup;
etching the conductive layers back from the hole;
etching the sacrificial layers back from the hole;
forming a blocking dielectric film inside at least a portion of the hole, the blocking dielectric film no thicker than an individual sacrificial layer of the sacrificial layers;
creating floating gates in the cavities created by the etching of the conductive layers and the sacrificial layers, the floating gates separated from the conductive layers and the tier insulating layers by the blocking dielectric film;
forming a tunneling dielectric film inside the hole; and
filling the hole with semiconductor material, the semiconductor material separated from the floating gates by the tunneling dielectric film.
10. The method of claim 9 , the conductive layers, the floating gates and the semiconductor material comprise polysilicon, and the tier insulating layers and the sacrificial layers comprise an oxide.
11. The method of claim 9 , further comprising:
creating an outer oxide film on an exposed area of the conductive layers after the etching of the conductive layers;
the blocking dielectric film includes a high dielectric film and an inner oxide film, the high dielectric film having a higher dielectric constant than the inner and outer oxide films; and
the conductive layers separated from the floating gates by an inter-poly dielectric includes the high dielectric film sandwiched between the outer oxide film and the inner oxide film.
12. The method of claim 11 , the high dielectric film comprising a nitride.
13. The method of claim 12 , comprising the high dielectric film sandwiched between the outer oxide film and the inner oxide film forming respective oxide-nitride-oxide (ONO) inter-poly dielectrics (IPDs) to separate respective control gates formed in respective conductive layers from respective floating gates.
14. The method of claim 13 , comprising respective control gates are no thicker than respective floating gates and the respective control gates are self-aligned with the respective floating gates.
15. The method of claim 11 , the inner and outer oxide film comprise silicon oxide, and the high dielectric film comprises silicon nitride, aluminum oxide, hafnium oxide, or hafnium silicate.
16. The method of claim 11 , creating the stackup comprises use of different materials for the sacrificial layers and for the tier insulating layers to differentiate the sacrificial layers from the tier insulating layers.