Voltage ramping detection

1. A method for detecting voltage ramping to a target voltage level, comprising:

ramping a regulated voltage to a steady state target voltage for an operation of a load circuit, the steady state target voltage being a voltage level that enables the load circuit to perform the operation;

generating an output signal indicating that the regulated voltage has reached the target voltage;

triggering a voltage regulation circuit with the output signal to regulate the regulated voltage to the target voltage; and

triggering a detection circuit with the output signal to generate a ready signal in response to the output signal indicating that the regulated voltage has reached the target voltage, wherein the ready signal is to cause the load circuit to perform the operation;

wherein triggering the detection circuit to generate the ready signal further comprises activating a first transistor of the voltage regulation circuit and a second transistor of the detection circuit with the output signal, wherein the first transistor and the second transistor are matched transistors.

2. The method of claim 1 , wherein the ready signal to cause the load circuit to perform the operation includes causing the load circuit to perform a write operation of a nonvolatile memory based on the ready signal.

3. The method of claim 1 , wherein generating the output signal further comprises comparing a feedback signal associated with the regulated voltage to a reference voltage and generating the output signal if the feedback signal exceeds the reference voltage.

4. The method of claim 1 , wherein the ready signal is to reach a voltage level to cause the load circuit to perform the operation at a time corresponding to the load circuit reaching the target voltage for performance of the operation.

5. The method of claim 1 , wherein the load circuit comprises a wordline or a bitline in a NAND memory device.

6. A circuit to detect voltage ramp-up to a target voltage, comprising:

a voltage regulator configured to:

generate a regulated voltage from a supply voltage, the supply voltage to ramp up from below a steady state target voltage to above the target voltage, the target voltage being a voltage level to enable a load circuit to perform an operation; and

generate an output signal in response to a ramp up of the regulated voltage to the target voltage, the output signal to trigger a voltage regulation circuit to begin regulation of the supply voltage to the target voltage; and

a voltage ramp-up detection circuit coupled to the voltage regulator, wherein the voltage ramp-up detection circuit is configured to:

detect the output signal, and

responsive to detection of a level of the output signal to indicate that the regulated voltage has reached the target voltage, generate a ready signal to cause the load circuit to perform the operation;

wherein the output signal is to be supplied to a first transistor within the voltage regulation circuit and a second transistor within the voltage ramp-up detection circuit, wherein the second transistor is matched to the first transistor.

7. The circuit of claim 6 , wherein the voltage regulator includes a comparator configured to generate the output signal when the regulated voltage has reached the target voltage.

8. The circuit of claim 7 , wherein the comparator is configured to compare a voltage reference signal with a voltage feedback signal to detect whether the regulated voltage has reached the target voltage, wherein the voltage feedback signal is configured to increase in proportion to the regulated voltage and exceed the voltage reference signal upon ramp up of the supply voltage to the regulated voltage.

9. The circuit of claim 8 , wherein the feedback voltage comprises a signal produced at a common node of a voltage divider coupled between the regulated voltage and a low voltage rail.

10. The circuit of claim 6 , wherein the voltage ramp-up detection circuit is held in an ON state by a low current bias.

11. The circuit of claim 6 , wherein the voltage ramp-up detection circuit generates the ready signal responsive to activation of the second transistor.

12. The circuit of claim 6 , wherein the voltage ramp-up detection circuit further comprises an inverter coupled to the second transistor, the inverter configured to generate the ready signal.

13. The circuit of claim 6 , wherein the first and second transistors include N-type metal-oxide-semiconductor logic (NMOS) devices.

14. The circuit of claim 6 , wherein the load circuit comprises a wordline or a bitline in a NAND memory device.

15. An electronic device comprising:

a memory subsystem including

a memory device having multiple physical rows of memory cells;

a voltage regulator coupled to the memory device to provide a write voltage to write a row of the memory cells, the voltage regulator to

generate a regulated voltage at a steady state target voltage for an operation of a load circuit from a supply voltage to be ramped up from below the target voltage to above the target voltage, the target voltage being a voltage level to enable the load circuit to perform the operation;

generate an output signal in response to a ramp up of the regulated voltage to the target voltage, the output signal to trigger a voltage regulation circuit to begin regulation of the supply voltage to the target voltage; and

a voltage ramp-up detection circuit coupled to the voltage regulator, wherein the voltage ramp-up detection circuit is configured to detect the output signal, and responsive to detection of a level of the output signal to indicate that the regulated voltage has reached the target voltage, generate a ready signal to a controller to cause the load circuit to perform the operation;

wherein the output signal is to be supplied to a first transistor of the voltage regulation circuit and a second transistor of the voltage ramp-up detection circuit, wherein the first transistor and the second transistor are matched.

16. The electronic device of claim 15 , wherein the voltage regulator further comprises a comparator circuit to compare a voltage reference signal with a voltage feedback signal, wherein the voltage feedback signal is configured increase in proportion to the regulated voltage and exceed the voltage reference signal upon ramp up of the supply voltage to the regulated voltage.