Methods and apparatus to read memory cells based on clock pulse counts

1. A method to program memory cells, comprising:

determining programmed states of a plurality of memory cells based on a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cells;

determining, based on the programmed states, first ones of the memory cells that do not satisfy a target threshold voltage; and

performing a programming pass on the first ones of the memory cells.

2. A method of claim 1 , further including determining a program pulse-type for use with the performing of the programming pass on the first ones of the memory cells, the program pulse-type determined based on analyzing the programmed states of the first ones of the memory cells relative to the target threshold voltage.

3. A method of claim 2 , wherein the program pulse-type is selected to be a full program pulse or a partial program pulse.

4. A method of claim 1 , further including:

determining, based on the programmed states, second ones of the memory cells that satisfy the target threshold voltage; and

inhibiting the second ones of the memory cells from the programming pass based on ones of the programmed states corresponding to the second ones of the memory cells satisfying the target threshold voltage.

5. A method of claim 1 , further including starting the counter in association with activating the plurality of memory cells.

6. A method of claim 1 , wherein the memory cells store multiple bits per memory cell.

7. A method of claim 1 , wherein the target threshold voltage is representative of data to be stored in the memory cells.

8. A method of claim 1 , wherein the memory cells are NAND flash memory.

9. An apparatus to program memory cells, comprising:

a programmed state detector to determine programmed states of a plurality of memory cells based on a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cells;

an analyzer to determine, based on the programmed states, first ones of the memory cells that do not satisfy a target threshold voltage; and

a circuit to perform a programming pass on the first ones of the memory cells.

10. An apparatus of claim 9 , wherein the analyzer is further to determine a program pulse-type for use with the performing of the programming pass on the first ones of the memory cells, the program pulse-type determined based on analyzing the programmed states of the first ones of the memory cells relative to the target threshold voltage.

11. An apparatus of claim 10 , wherein the analyzer is to select the program pulse-type to be a full program pulse or a partial program pulse.

12. An apparatus of claim 9 , wherein the analyzer is further to:

determine, based on the programmed states, second ones of the memory cells that satisfy the target threshold voltage; and

determine to inhibit the second ones of the memory cells from the programming pass based on ones of the programmed states corresponding to the second ones of the memory cells satisfying the target threshold voltage.

13. An apparatus of claim 9 , wherein the counter is to reach the trigger count value after starting in association with activating the plurality of memory cells.

14. An apparatus of claim 9 , wherein the memory cells store multiple bits per memory cell.

15. An apparatus of claim 9 , wherein the target threshold voltage is representative of data to be stored in the memory cells.

16. An apparatus of claim 9 , wherein the memory cells are NAND flash memory.

17. At least one article of manufacture comprising machine readable instructions that, when executed, cause a memory controller to at least:

determine programmed states of a plurality of memory cells based on a counter reaching a trigger count value;

associate ones of the memory cells with different regions of a soft bit range based on the programmed states; and

redefine boundary reference voltages of threshold voltage ranges corresponding to the memory cells based on a distribution of the ones of the memory cells across the regions of the soft bit range.

18. At least one article of manufacture of claim 17 , wherein the instructions are further to cause the memory controller to select the trigger count value from a plurality of different trigger count values based on a characteristic of the memory cells.

19. At least one article of manufacture of claim 17 , wherein the soft bit range is between first and second boundary reference voltages, the first boundary reference voltage to represent a first binary value, and the second boundary reference voltage to represent a second binary value.

20. At least one article of manufacture of claim 19 , wherein the redefining of the boundary reference voltages of the threshold voltage ranges aligns the ones of the memory cells with representing the first binary value or the second binary value.

21. At least one article of manufacture of claim 17 , wherein the instructions are further to cause the memory controller to start the counter in association with activating the plurality of memory cells.

22. At least one article of manufacture of claim 17 , wherein the memory cells store multiple bits per memory cell.

23. At least one article of manufacture of claim 17 , wherein the memory cells are NAND flash memory.

24. At least one article of manufacture comprising machine readable instructions that, when executed, cause a memory controller to at least:

determine programmed states of a plurality of memory cells based on a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cells;

determine, based on the programmed states, first ones of the memory cells that do not satisfy a target threshold voltage; and

perform a programming pass on the first ones of the memory cells.

25. At least one article of manufacture of claim 24 , wherein the instructions are further to cause the memory controller to determine a program pulse-type for use with the performing of the programming pass on the first ones of the memory cells, the program pulse-type determined based on analyzing the programmed states of the first ones of the memory cells relative to the target threshold voltage.

26. At least one article of manufacture of claim 25 , wherein the program pulse-type is selected to be a full program pulse or a partial program pulse.

27. At least one article of manufacture of claim 24 , wherein the instructions are further to cause the memory controller to:

determine, based on the programmed states, second ones of the memory cells that satisfy the target threshold voltage; and

inhibit the second ones of the memory cells from the programming pass based on ones of the programmed states corresponding to the second ones of the memory cells satisfying the target threshold voltage.

28. At least one article of manufacture of claim 24 , wherein the instructions are further to cause the memory controller to start the counter in association with activating the plurality of memory cells.

29. At least one article of manufacture of claim 24 , wherein the memory cells store multiple bits per memory cell.

30. At least one article of manufacture of claim 24 , wherein the target threshold voltage is representative of data to be stored in the memory cells.

31. At least one article of manufacture of claim 24 , wherein the memory cells are NAND flash memory.

32. A method to program memory cells, comprising:

determining programmed states of a plurality of memory cells based on a counter reaching a trigger count value;

associating ones of the memory cells with different regions of a soft bit range based on the programmed states; and

redefining boundary reference voltages of threshold voltage ranges corresponding to the memory cells based on a distribution of the ones of the memory cells across the regions of the soft bit range.

33. A method of claim 32 , further including selecting the trigger count value from a plurality of different trigger count values based on a characteristic of the memory cells.

34. A method of claim 32 , wherein the soft bit range is between first and second boundary reference voltages, the first boundary reference voltage to represent a first binary value, and the second boundary reference voltage to represent a second binary value.

35. A method of claim 34 , wherein the redefining of the boundary reference voltages of the threshold voltage ranges aligns the ones of the memory cells with representing the first binary value or the second binary value.

36. A method of claim 32 , further including starting the counter in association with activating the plurality of memory cells.

37. A method of claim 32 , wherein the memory cells store multiple bits per memory cell.

38. A method of claim 32 , wherein the memory cells are NAND flash memory.

39. An apparatus to program memory cells, comprising:

a programmed state detector to:

determine programmed states of a plurality of memory cells based on a counter reaching a trigger count value; and

associate ones of the memory cells with different regions of a soft bit range based on the programmed states; and

a circuit to redefine boundary reference voltages of threshold voltage ranges corresponding to the memory cells based on a distribution of the ones of the memory cells across the regions of the soft bit range.

40. An apparatus of claim 39 , further including a trigger value retriever to select the trigger count value from a plurality of different trigger count values based on a characteristic of the memory cells.

41. An apparatus of claim 39 , wherein the soft bit range is between first and second boundary reference voltages, the first boundary reference voltage to represent a first binary value, and the second boundary reference voltage to represent a second binary value.

42. An apparatus of claim 41 , wherein the redefining of the boundary reference voltages of the threshold voltage ranges aligns the ones of the memory cells with representing the first binary value or the second binary value.

43. An apparatus of claim 39 , wherein the circuit is to start the counter in association with activating the plurality of memory cells.

44. An apparatus of claim 39 , wherein the memory cells store multiple bits per memory cell.

45. An apparatus of claim 39 , wherein the memory cells are NAND flash memory.