IP Library Granted Patent US 9,659,613
Granted Patent B1
US 9,659,613 · App. 15/347,571 · Granted May 23, 2017

Methods and apparatus to read memory cells based on clock pulse counts

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Quick Facts
Patent No.
US 9,659,613
App. No.
15/347,571
Granted
May 23, 2017
Kind
B1
Abstract

A disclosed example accesses a binary value latched by a sense amplifier in circuit with a memory cell, the binary value latched by the sense amplifier in response to a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cell; determines a programmed state of the memory cell based on the binary value; and performs a memory operation based on the programmed state of the memory cell.

Claims (30)

1. A method to access a programmed state of a memory cell, the method comprising:

accessing a binary value latched by a sense amplifier in circuit with the memory cell, the binary value latched by the sense amplifier in response to a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cell;

determining the programmed state of the memory cell based on the binary value; and

performing a memory operation based on the programmed state of the memory cell.

2. A method of claim 1 , further including starting the counter at a first time before the binary value is latched by the sense amplifier, the binary value latched by the sense amplifier at a second time when the counter reaches the trigger count value.

3. A method of claim 1 , wherein performing the memory operation includes performing a programming pass on the memory cell to program the memory cell to a target threshold voltage.

4. A method of claim 1 , wherein performing the memory operation includes determining a program pulse-type for use with performing a programming pass on the memory cell to program the memory cell to a target threshold voltage.

5. A method of claim 4 , wherein the program pulse-type is selected to be a full program pulse or a partial program pulse.

6. A method of claim 1 , wherein performing the memory operation includes writing data to a data bus based on the programmed state of the memory cell.

7. A method of claim 1 , wherein the characteristic of the memory cell is at least one of a temperature of the memory cell, a temperature coefficient of the memory cell, or a location of the memory cell in a memory cell array.

8. An apparatus to access a programmed state of a memory cell, the apparatus comprising:

a sense amplifier in circuit with the memory cell to latch a binary value in response to a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cell;

a programmed state detector to determine the programmed state of the memory cell based on the binary value; and

a circuit to perform a memory operation based on the programmed state of the memory cell.

9. An apparatus of claim 8 , further including the counter to start at a first time before the binary value is latched by the sense amplifier, the binary value to be latched by the sense amplifier at a second time when the counter reaches the trigger count value.

10. An apparatus of claim 8 , wherein the circuit is to perform the memory operation by performing a programming pass on the memory cell to program the memory cell to a target threshold voltage.

11. The apparatus of claim 8 , wherein the circuit is to perform the memory operation by determining a program pulse-type for use with performing a programming pass on the memory cell to program the memory cell to a target threshold voltage.

12. The apparatus of claim 11 , wherein the program pulse-type is selected to be a full program pulse or a partial program pulse.

13. The apparatus of claim 8 , wherein the circuit is to perform the memory operation by writing data to a data bus based on the programmed state of the memory cell.

14. The apparatus of claim 8 , wherein the characteristic of the memory cell is at least one of a temperature of the memory cell, a temperature coefficient of the memory cell, or a location of the memory cell in a memory cell array.

15. At least one article of manufacture comprising machine readable instructions that, when executed, cause a memory controller to at least:

access a binary value latched by a sense amplifier in circuit with a memory cell, the binary value latched by the sense amplifier in response to a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cell;

determine a programmed state of the memory cell based on the binary value; and

perform a memory operation based on the programmed state of the memory cell.

16. At least one article of manufacture of claim 15 , wherein the instructions are further to cause the memory controller to start the counter at a first time before the binary value is latched by the sense amplifier, the binary value latched by the sense amplifier at a second time when the counter reaches the trigger count value.

17. At least one article of manufacture of claim 15 , wherein the instructions are to cause the memory controller to perform the memory operation by performing a programming pass on the memory cell to program the memory cell to a target threshold voltage.

18. At least one article of manufacture of claim 15 , wherein the instructions are to cause the memory controller to perform the memory operation by determining a program pulse-type for use with performing a programming pass on the memory cell to program the memory cell to a target threshold voltage.

19. At least one article of manufacture of claim 18 , wherein the program pulse-type is selected to be a full program pulse or a partial program pulse.

20. At least one article of manufacture of claim 15 , wherein the instructions are to cause the memory controller to perform the memory operation by writing data to a data bus based on the programmed state of the memory cell.

21. At least one article of manufacture of claim 15 , wherein the characteristic of the memory cell is at least one of a temperature of the memory cell, a temperature coefficient of the memory cell, or a location of the memory cell in a memory cell array.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2023
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 064928/0832 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2016
From: PAN, FENG; GHODSI, RAMIN
To: INTEL CORPORATION
Reel/Frame 040598/0869 →