Tungsten salicide gate source for vertical NAND string to control on current and cell pillar fabrication
View Patent ↗A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired floating gate that is formed when an Al oxide etch-stop layer is conventionally used.
1. A memory device, comprising:
a channel comprising a first end and a second end, the first end of the channel being coupled to a bit line and the second end of the channel being coupled to a source;
a select gate formed at the second end of the channel to selectively control conduction between the bit line and the channel, the select gate comprising a layer of tungsten salicide;
at least one non-volatile memory cell formed along a length of the channel between the select gate and the first end of the channel; and
at least one word line coupled to the at least one non-volatile memory cell;
wherein a distance between the select gate and the at least one word line is reduced with respect to a memory device having a select gate comprising aluminum oxide.
2. The memory device according to claim 1 , wherein the at least one non-volatile memory cell comprises a floating-gate (FG) memory cell or a charge trap flash (CTF) memory cell.
3. The memory device according to claim 1 , wherein the memory device comprises part of a solid-state drive (SSD).
4. The memory device according to claim 1 , wherein the memory device comprises part of an array of memory devices.
5. The memory device according to claim 1 , wherein the select gate comprises a layer of tungsten salicide formed between two polysilicon layers.
6. A memory device, comprising:
a channel comprising a first end and a second end, the first end of the channel being coupled to a bit line and the second end of the channel being coupled to a source;
a select gate formed at the second end of the channel to selectively control conduction between the bit line and the channel, the select gate comprising a layer of tungsten salicide;
the select gate being adjacent to a layer of polysilicon;
at least one non-volatile memory cell formed along a length of the channel between the select gate and the first end of the channel; and
at least one word line coupled to the at least one non-volatile memory cell;
wherein a distance between the select gate and the at least one word line is reduced with respect to a memory device having a select gate comprising aluminum oxide.
7. The memory device according to claim 6 , wherein the at least one non-volatile memory cell comprises a floating-gate (FG) memory cell or a charge trap flash (CTF) memory cell.
8. The memory device according to claim 6 , wherein the memory device comprises part of a solid-state drive (SSD).
9. The memory device according to claim 6 , wherein the memory device comprises part of an array of memory devices.
10. The memory device according to claim 6 , wherein the select gate comprises a layer of tungsten salicide formed between two polysilicon layers.