Apparatus and methods for improved flash cell characteristics
View Patent ↗Embodiments of an apparatus and methods for providing improved flash memory cell characteristics are generally described herein. Other embodiments may be described and claimed.
1. A method of forming a memory cell, comprising:
forming an active region on a substrate;
forming a tunnel dielectric on the active region;
forming a floating gate on the tunnel dielectric, wherein the floating gate comprises a first portion and a second portion;
forming continuous isolation regions on the substrate directly adjacent to the active region, the tunnel dielectric, and along a side the first portion of the floating gate;
forming a conformal dielectric layer directly adjacent to the floating gate and the isolation regions, and;
forming a p-doped control gate on the conformal dielectric layer and between the floating gates, wherein the p-doped control gate extends below a top surface of the floating gate.
2. The method of claim 1 , wherein the p-doped control gate is doped with a group III element of the group consisting of boron (B), aluminum (Al), gallium (Ga) and indium (In).
3. The method of claim 2 , wherein the p-doped control gate is doped between 5E19 atoms/cm^3 and the solid solubility limit.
4. The method of claim 1 , further comprising thermally annealing the p-doped control gate.
5. The method of claim 1 , further comprising applying a bias across the tunnel dielectric to store electrons in the floating gate.
6. The method of claim 5 , wherein the memory cell is programmed without forming a depletion region across the p-doped control gate that extends below the top surface of the floating gate.
7. The method of claim 1 , wherein a space between the floating gate and a second floating gate is substantially equal to 50 nm or less.
8. A non-volatile memory, comprising:
an isolation region on a substrate;
a tunnel dielectric on the active region;
a floating gate on the tunnel dielectric;
an isolation region on the substrate directly adjacent to the active region, the tunnel dielectric, and along a side of a portion of the floating gate;
a conformal dielectric layer directly adjacent to the floating gate and the isolation region;
a p-doped control gate on the dielectric layer and between the floating gate wherein the p-doped control gate extends below a top surface of the floating gate to provide a p-doped control gate finger between the floating gate and a second floating gate.
9. The non-volatile memory of claim 8 , wherein the p-doped control gate is doped with a group III element of the group consisting of boron (B), aluminum (Al), gallium (Ga) and indium (In).
10. The non-volatile memory of claim 9 , wherein the p-doped control gate is doped between 5E19 atoms/cm^3 and the solid solubility limit.
11. The non-volatile memory of claim 8 , wherein the p-doped control gate is thermally annealed.
12. The non-volatile memory of claim 8 , the floating gate further comprising a first portion and a second portion.
13. The non-volatile memory of claim 12 , wherein the isolation region is formed along a side of the first portion of the floating gate.
14. A communications system, comprising:
a motherboard;
a central processing unit; and
a memory, the memory comprising;
a pair of spaced apart isolation regions formed in a substrate and defining a substrate active region there between;
a tunnel dielectric formed on the active region;
a floating gate formed on the tunnel dielectric;
a dielectric layer on the floating gates and the isolation regions, wherein the dielectric layer is directly adjacent to a top surface of the floating gate and along sides of the floating gate and wherein the isolation regions are positioned directly adjacent to a portion of the floating gate;
a p-doped control gate on the dielectric layer and between the floating gate and another floating gate positioned on another active region and tunnel dielectric, wherein the p-doped control gate is positioned below the top surface of the floating gate.
15. The communications system of claim 14 , wherein the p-doped control gate is doped with a group III element of the group consisting of boron (B), aluminum (Al), gallium (Ga) and indium (In).
16. The communications system of claim 14 , wherein the p-doped control gate is doped between 5E19 atoms/cm^3 and the solid solubility limit.
17. The communications system of claim 14 , wherein the p-doped control gate is thermally annealed.
18. The communications system of claim 14 , wherein the communications system is selected from the group consisting of a mobile device, a tablet computing device, a laptop computing device, a desktop computing device, a set-top box, an entertainment control unit, and a digital camera.
19. The communications system of claim 14 , wherein a space between the floating gates is substantially equal to 50 nm or less.
20. The communications system of claim 14 , wherein the p-doped control gate comprises polysilicon.