N plane to 2N plane interface in a solid state drive (SSD) architecture
View Patent ↗A solid state drive includes a controller with a hardware interface to fewer planes of memory cells than included in the nonvolatile storage. For example, a controller hardware interface can include a 1N plane interface coupled to a nonvolatile storage device with 2N planes of memory cells. For data access transactions between the controller and the nonvolatile storage device, first and second consecutive 1N plane command sequences are interpreted as a single 2N plane command sequence.
1. A solid state drive comprising:
a nonvolatile storage device including a second number of planes of memory cells; and
a controller including a hardware interface coupled to the nonvolatile storage device, the hardware interface to provide access to a first number of planes of memory cells in the nonvolatile storage device, the first number of planes of memory cells being different than the second number of planes of memory cells;
wherein a data access transaction between the controller and the nonvolatile storage device includes first and second consecutive command sequences, each pair of the first and second command sequences to access the first number of planes of memory cells collectively being interpreted as a single command sequence to access the second number of planes of memory cells, and
wherein the nonvolatile storage device to ignore a first execute command associated with the first command sequence, and to execute the first and second command sequences in response to a second execute command associated with the second command sequence.
2. The solid state drive of claim 1 , wherein the nonvolatile storage device comprises a quad-plane storage device, and wherein the controller includes a dual-plane hardware interface.
3. The solid state drive of claim 1 , wherein the data access transaction comprises a write from the controller to the nonvolatile storage device.
4. The solid state drive of claim 3 , further comprising the controller to set the nonvolatile storage device to a first configuration prior to the first command sequence, and to set the nonvolatile storage device to a second configuration between the first command sequence and the second command sequence.
5. The solid state drive of claim 1 , wherein the execute command comprises a confirm command.
6. The solid state drive of claim 1 , wherein the data access transaction comprises a read from the nonvolatile storage device to the controller.
7. The solid state drive of claim 6 , further comprising the nonvolatile storage device to generate first and second command sequences, each of the first and second command sequences to access the first number of planes of memory cells to transfer the second number of planes of memory cells of data to the controller.
8. The solid state drive of claim 6 , further comprising the nonvolatile storage device to send a third command sequence to access the second number of planes of memory cells, which the controller interprets as a pair of first and second command sequences, each one of the first command sequence and the second command sequence to access the first number of planes of memory cells.
9. A computing system, comprising:
a multicore processor to execute instructions;
a volatile memory device to store data to be executed by the processor; and
a solid state drive coupled to the processor and the volatile memory device, the solid state drive including
a nonvolatile storage device including a second number of planes of memory cells; and
a controller including a hardware interface coupled to the nonvolatile storage device, the hardware interface to provide access to a first number of planes of memory cells in the nonvolatile storage device, the first number of planes of memory cells being different than the second number of planes of memory cells;
wherein a data access transaction between the controller and the nonvolatile storage device includes first and second consecutive command sequences, each pair of the first and second command sequences to access the first number of planes of memory cells collectively being interpreted as a single command sequence to access the second number of planes of memory cells; and
wherein the nonvolatile storage device to ignore a first execute command associated with the first command sequence, and to execute the first and second command sequences in response to a second execute command associated with the second command sequence.
10. The computing system of claim 9 , wherein the data access transaction comprises a write from the controller to the nonvolatile storage device, and further comprising the controller to set the nonvolatile storage device to a first configuration prior to the first command sequence, and to set the nonvolatile storage device to a second configuration between the first command sequence and the second command sequence.
11. The computing system of claim 9 , wherein the data access transaction comprises a write from the controller to the nonvolatile storage device.
12. The computing system of claim 9 , wherein the data access transaction comprises a read from the nonvolatile storage device to the controller, and further comprising the nonvolatile storage device to generate a pair of first and second command sequences, each one of the first command sequence and the second command sequence to access the first number of planes of memory cells to collectively transfer the second number of planes of memory cells of data to the controller.
13. The computing system of claim 9 , further comprising one or more of
a network adapter coupled to exchange data between the memory modules and a remote network location;
a display communicatively coupled to the processor; or,
a battery to power the computing system.
14. A method for storing data, comprising:
sending a first configuration setting from a controller having a hardware interface to a nonvolatile storage device, the hardware interface to provide access to a first number of planes of memory cells of the nonvolatile storage device, the nonvolatile storage device having a second number of planes of memory cells, prior to a first data access transaction to cause the nonvolatile storage device to ignore an execute command of the first data access transaction;
sending a first data access transaction from the controller to the nonvolatile storage device, wherein the first data access transaction to address the first number of planes of memory cells, the first number of planes of memory cells being different than the second number of planes of memory cells; and
sending a consecutive second data access transaction to address the first number of planes of memory cells from the controller to the nonvolatile storage device;
wherein the nonvolatile storage device to interpret the consecutive first and second data access transactions as a third data access transaction to access the second number of planes of memory cells.
15. The method of claim 14 , wherein the second number of planes of memory cells is twice the first number of planes of memory cells.
16. The method of claim 14 , further comprising:
sending a second configuration setting from the controller to the nonvolatile storage device between the first data access transaction and the second data access transaction to cause the nonvolatile storage device to execute an execute command of the second data access transaction.
17. The method of claim 14 , wherein sending the first configuration setting is to cause the nonvolatile storage device to ignore a confirm command of the first data access transaction.
18. The method of claim 14 , wherein sending the first configuration setting is to cause the nonvolatile storage device to ignore the execute command of the first data access transaction and automatically clear the first configuration setting.