Nibble encoding for improved reliability of non-volatile memory
View Patent ↗A wireless device to include a non-volatile memory to execute an encoding scheme to provide single-cell error detection and correction on program operations in which the initial nibble value is Fh and on program operations that result in a nibble value of 0h. The non-volatile memory uses multiple writes to program a nibble more than once with non-zero data between erase cycles.
1. An apparatus comprising:
a multicore processor; and
a non-volatile memory device having a plurality of multilevel memory cells and an encoder controller to:
choose a set of first-write nibble codes for an encoding scheme so that no more than one level value stored in a multilevel memory cell of a given nibble code can match a level value in corresponding multilevel memory cells of other nibble codes included in the set of first-write nibble codes and a subset of the set of first-write nibble codes are rewritable to multiple different non-zero nibble codes; and
use the encoding scheme to provide first-write error protection to a four-bit boundary on the non-volatile memory device.
2. The apparatus of claim 1 , comprising one or more of the multiple different non-zero nibble codes successively rewritable to two different non-zero codes.
3. The apparatus of claim 1 , comprising the encoder controller to ensure that all of the nibble codes in the subset of first-write nibble codes are rewritten to nibble codes that are one-cell-error nibble codes of first-write nibble codes with same nibble values.
4. The apparatus of claim 1 , comprising the encoder controller to ensure that a nibble code is not a one-cell-error nibble code of any of the set of first-write nibble codes.
5. The apparatus of claim 1 , multiple first-write nibble codes other than those in the subset of first-write nibble codes are rewritable to two different non-zero nibble codes.
6. The apparatus of claim 1 , all but a single nibble code of the first-write nibble codes are rewritable to the single nibble code.
7. The apparatus of claim 6 , the single nibble code is a zero nibble code.
8. A method comprising:
choosing, at an encoder controller for a non-volatile memory device, a set of first-write nibble codes for an encoding scheme, the set chosen so that no more than one level value stored in a multilevel memory cell of a given nibble code can match a level value in corresponding multilevel memory cells of other nibble codes included in the set and a subset of the set of first-write nibble codes are rewritable to multiple different non-zero nibble codes; and
using the encoding scheme to provide first-write error protection to a four-bit boundary on the non-volatile memory device.
9. The method of claim 8 , comprising one or more of the multiple different non-zero nibble codes successively rewritable to two different non-zero codes.
10. The method of claim 8 comprising:
ensuring that all of the nibble codes in the subset of first-write nibble codes are rewritten to nibble codes that are one-cell-error nibble codes of first-write nibble codes with same nibble values.
11. The method of claim 10 , the set of first-write nibble codes comprises sixteen first-write nibble codes, each first-write nibble code to include a given nibble value from 0h to Fh.
12. The method of claim 11 , the subset comprises four first-write nibble codes having nibble code values of Eh, Dh, Bh, and 7h.
13. The method of claim 11 , six first-write nibble codes from the set of first-write nibble codes other than those in the subset are rewritable to two different non-zero codes, the six first-write nibble codes having nibble code values of Ch, 9h, 6h, 5h, and 3h.
14. The method of claim 8 comprising:
ensuring that a nibble code is not a one-cell-error nibble code of any of the set of first-write nibble codes.
15. The method of claim 8 , all but a single nibble code of the first-write nibble codes are rewritable to the single nibble code.
16. The method of claim 15 , the single nibble code is a zero nibble code.
17. A system comprising:
a wireless interface having an antenna;
a multicore processor; and
a non-volatile memory having multilevel memory cells and an encoder controller to provide first-write error protection to a four-bit boundary for first-write nibble codes programmed to the multilevel memory cells, each of the multilevel memory cells placeable into any of more than two charge states, each first-write nibble code including four code cells, each code cell corresponding to a multilevel memory cell and comprising a level value included in a set of more than two level values corresponding to the more than two charge states, each level value in the set of more than two level values corresponding to one of the more than two charge states.
18. The system of claim 17 , the encoder controller to program bit pairs with single-cell error detection and correction for every program operation.
19. The system of claim 17 , the encoder controller to execute an encoding scheme that has bit twiddle programming granularity.
20. The system claim 17 , the encoder controller to perform single-cell error detection and correction on a first write to a nibble and transition writes that bring a value for the nibble to a zero value.