Memory array with pseudo single bit memory cell and method
View Patent ↗In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The output of the cell or cells associated with the flag cell is a single bit when the flag cell is set. The cell or cells associated with the flag cell operate as multi level/bit per cell cells when the flag cell is not set. The flag cell of the memory array may also be a multi level/bit per cell cell that is read to provide a single bit output. Multiple flag cells may be provided and associated with various cells or groups of cells so that these cells or groups of cells may be operated in a user selectable pseudo single bit configuration.
1. A method of reading a first memory cell, the method comprising:
reading a flag cell that is associated with the first memory cell, the flag cell being settable between a multi bit per cell position and a single bit per cell position; and
reading the first memory cell and providing an output, the output being a multi bit output when the flag cell is in the multi bit per cell position and a pseudo single bit output when the flag cell is in the single bit per cell position, the pseudo single bit output being the multi bit output masked to represent a single bit.
2. The method of claim 1 , wherein the step of reading the first memory cell comprises reading a single bit output specific voltage threshold of the first memory cell when the flag cell is in the single bit per cell position.
3. The method of claim 1 , wherein a plurality of memory cells are associated with the flag cell, and wherein the step of reading the first memory cell and providing an output comprises reading the plurality of memory cells and providing an output corresponding to each memory cell of the plurality of memory cells as the multi bit output when the flag cell is in the multi bit per cell position and the single bit output when the flag cell is in the single bit per cell position.
4. The method of claim 1 , further comprising the steps of
reading a second flag cell that is associated with a second memory cell, the second flag cell being settable between the multi bit per cell position and the single bit per cell position;
reading the second memory cell and providing a second output, the second output being the multi bit output when the second flag cell is in the multi bit per cell position and the single bit output when the second flag cell is in the single bit per cell position.