Repurposing NAND ready/busy pin as completion interrupt
View Patent ↗A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.
1. A system comprising:
a plurality of NAND memory devices, each NAND memory device having Ready/Busy contact, and memory logic to,
receive a command to execute an operation,
determine that execution of the operation has completed, and
pulse the Ready/Busy contact of the memory device in response to determining that execution of the operation has completed; and
a host device including a Ready/Busy contact coupled to the Ready/Busy contact of each NAND memory device, and host logic to,
detect the pulse on the Ready/Busy contact of the host device, and
issue a read status enhanced command to each of the plurality of NAND memory devices in response to detecting the pulse.
2. The system of claim 1 , wherein each memory device further includes a status register, the memory logic to access the status register and pulse the Ready/Busy contact of the memory device if a ready bit of the status register is set.
3. The system of claim 2 , wherein the ready bit is an array ready bit.
4. The system of claim wherein the memory logic is to pulse the Ready/Busy contact of the memory device low for approximately 100 nanoseconds.
5. The system of claim 4 , wherein the memory logic is to maintain the Ready/Busy contact of the memory device high until execution of the operation has completed.
6. The system of claim 1 , wherein the host device is to issue the command to execute the operation.
7. The system of claim 6 , wherein the operation includes at least one of a program, read and erase operation.
8. A method of operating a host device comprising:
issuing a command to perform an operation on one or more of a plurality of flash memory devices coupled to a Ready/Busy contact of the host device;
detecting a pulse on the Read/Busy contact of the host device; and
issuing a read status enhanced command to each of the plurality of flash memory devices in response to detecting the pulse.
9. The method of claim 8 , wherein the detecting includes detecting a low pulse on the Ready/Busy contact.
10. The method of claim 9 , wherein the low pulse has a duration of approximately 100 nanoseconds.
11. The method of claim 8 , wherein the flash memory devices include NAND devices and the operation includes at least one of a program, read and erase operation.