Compressing error vectors for decoding logic to store compressed in a decoder memory used by the decoding logic

1. An apparatus for decoding data, comprising:

a decoder to decode codewords to produce error vectors used to decode the codewords;

a decoder memory device to store the error vectors; and

a compression unit to:

receive an error vector from the decoder during decoding of a codeword, wherein each bit in the error vector has one of a first value and a second value;

determine at least one bit location in the error vector having the first value; and

store at least one pointer in a row of memory cells in the decoder memory device indicating the determined at least one bit location in the codeword having the first value.

2. The apparatus of claim 1 , wherein the row of memory cells is configured to store a maximum number of pointers to bit locations in the error vector having the first value that is less than a number of bits in the error vector to compress the error vector in the row of memory cells.

3. The apparatus of claim 2 , wherein the error vector has a sparse number of the first value.

4. The apparatus of claim 3 , wherein the decoder memory device is configured such that the row of memory cells is of sufficient width to store the maximum number of pointers to bit locations in the error vector a threshold percentage of a time based on a raw bit error rate supported by the decoder.

5. The apparatus of claim 4 , wherein the decoder comprises a bit-flip (BF) decoder to flip values in the codeword to decode to produce a noise-free and zero syndrome codeword with a sparse number of instances of the first value, wherein the BF decoder performs multiple iterations of generating error vectors to move toward a noise free codeword having zero syndrome, wherein each of the generated error vectors is sent to the compression unit to store the pointers for the bit locations in the generated error vectors having the first value in different rows of memory cells in the decoder memory device.

6. The apparatus of claim 2 , wherein the compression unit stores the pointers in the row of memory cells in the decoder memory device by further:

determine whether there are remaining pointers indicating bit locations in the error vector having the first value not yet stored in the decoder memory device after storing the maximum number of pointers for the error vector in the row of memory cells in the decoder memory device; and

store the remaining pointers in a next row of memory cells in the decoder memory device in response to determining that there are the remaining pointers not yet stored.

7. The apparatus of claim 6 , wherein the compression unit is further to:

indicate in an overflow register that the next row of memory cells in the decoder memory device following the row of memory cells in which the maximum number of pointers are stored includes further pointers for the error vector.

8. The apparatus of claim 7 , wherein the overflow register is stored in the decoder memory device and has a bit for each row of memory cells in the decoder memory device.

9. The apparatus of claim 1 , further comprising:

a decompression unit;

wherein the decoder is further to request, from the decompression unit, an error vector stored in the decoder memory device,

wherein the decompression unit is further to:

receive, from the decoder, the request for the error vector;

determine a row of memory cells in the decoder memory device for the requested error vector; and

reconstruct the requested error vector to include the first value in each of the bit locations indicated in the pointers in the determined row of memory cells, wherein bit locations in the requested error vector not identified in the pointers in the determined row of memory cells indicate the second value.

10. The apparatus of claim 9 , wherein the decompression unit is further to:

determine whether a next row of memory cells from the determined row includes pointers for the requested error vector; and

indicate in the error vector the first value in the bit locations indicated in pointers in the next row for the requested error vector.

11. The apparatus of claim 1 , wherein the decoder memory device comprises a static random access memory (SRAM).

12. A storage device, comprising:

storage units storing codewords;

a decoder to decode codewords to produce error vectors used to decode the codewords;

a decoder memory device to store the error vectors; and

a compression unit to:

receive an error vector from the decoder during decoding of a codeword, wherein each bit in the error vector has one of a first value and a second value;

determine at least one bit location in the error vector having the first value; and

store at least one pointer in a row of memory cells in the decoder memory device indicating the determined at least one bit location in the codeword having the first value.

13. The storage device of claim 12 , wherein the row of memory cells is configured to store a maximum number of pointers to bit locations in the error vector having the first value that is less than a number of bits in the error vector to compress the error vector in the row of memory cells.

14. The storage device of claim 13 , wherein the error vector has a sparse number of the first value.

15. The storage device of claim 14 , wherein the decoder memory device is configured such that the row of memory cells is of sufficient width to store the maximum number of pointers to bit locations in the error vector a threshold percentage of a time based on a raw bit error rate supported by the decoder.

16. The storage device of claim 13 , wherein the compression unit stores the pointers in the row of memory cells in the decoder memory device by further:

determine whether there are remaining pointers indicating bit locations in the error vector having the first value not yet stored in the decoder memory device after storing the maximum number of pointers for the error vector in the row of memory cells in the decoder memory device; and

store the remaining pointers in a next row of memory cells in the decoder memory device in response to determining that there are the remaining pointers not yet stored.

17. The storage device of claim 12 , further comprising:

a decompression unit;

wherein the decoder is further to request, from the decompression unit, an error vector stored in the decoder memory device,

wherein the decompression unit is further to:

receive, from the decoder, the request for the error vector;

determine a row of memory cells in the decoder memory device for the requested error vector; and

reconstruct the requested error vector to include the first value in bit locations indicated in the pointers in the determined row of memory cells, wherein bit locations in the requested error vector not identified in the pointers in the determined row of memory cells indicate the second value.

18. The storage device of claim 17 , wherein the decompression unit is further to:

determine whether a next row of memory cells from the determined row includes pointers for the requested error vector; and

indicate in the error vector the first value in the bit locations indicated in pointers in the next row for the requested error vector.

19. A method for decoding data, comprising:

decoding codewords to produce error vectors used to decode the codewords;

storing the error vectors in a decoder memory device;

receiving an error vector from the decoder during decoding of a codeword, wherein each bit in the error vector has one of a first value and a second value;

determining at least one bit location in the error vector having the first value; and

storing at least one pointer in a row of memory cells in the decoder memory device indicating the determined at least one bit location in the codeword having the first value.

20. The method of claim 19 , wherein the row of memory cells is configured to store a maximum number of pointers to bit locations in the error vector having the first value that is less than a number of bits in the error vector to compress the error vector in the row of memory cells.

21. The method of claim 20 , wherein the error vector has a sparse number of the first value.

22. The method of claim 21 , wherein the decoder memory device is configured such that the row of memory cells is of sufficient width to store the maximum number of pointers to bit locations in the error vector a threshold percentage of a time based on a raw bit error rate supported by the decoder.

23. The method of claim 20 , wherein the storing the pointers in the row of memory cells in the decoder memory device further comprises:

determining whether there are remaining pointers indicating bit locations in the error vector having the first value not yet stored in the decoder memory device after storing the maximum number of pointers for the error vector in the row of memory cells in the decoder memory device; and

storing the remaining pointers in a next row of memory cells in the decoder memory device in response to determining that there are the remaining pointers not yet stored.

24. The method of claim 19 , further comprising:

requesting an error vector stored in the decoder memory device;

receiving the request for the error vector;

determining a row of memory cells in the decoder memory device for the requested error vector; and

reconstructing the requested error vector to include the first value in bit locations indicated in the pointers in the determined row of memory cells, wherein bit locations in the requested error vector not identified in the pointers in the determined row of memory cells indicate the second value.

25. The method of claim 24 , further comprising:

determining whether a next row of memory cells from the determined row includes pointers for the requested error vector; and

indicating in the error vector the first value in the bit locations indicated in pointers in the next row for the requested error vector.