IP Library Assignment 049360/0426
Patent Assignment
Reel/Frame 049360/0426

Assignment of Assignor's Interest

Recorded: 2019-06-04 Pages: 5
Assignors
PALANGAPPA, POOVAIAH M.
Executed: 2019-05-22
KWOK, ZION S.
Executed: 2019-05-23
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Property (1)
Compressing Error Vectors for Decoding Logic to Store Compressed in a Decoder Memory Used by the Decoding Logic
Application: 16/422,891 →
Publication: US 2019/0280715
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Sep 17, 2023
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 064928/0832 →