Ordering of memory device mapping to reduce contention
View Patent ↗An embodiment of a semiconductor apparatus may include technology to determine a differentiator associated with an access request for two or more memory devices, and set a target order for the two or more memory devices based on the differentiator. Other embodiments are disclosed and claimed.
1. An electronic processing system, comprising:
a processor;
a memory component communicatively coupled to the processor, the memory component including two or more memory devices; and
logic communicatively coupled to the processor and the memory component to:
identify a differentiator associated with an access request for the two or more memory devices,
set a target order for the two or more memory devices based on the differentiator, and
set a position in the target order for one or more of the two or more memory devices to a pre-determined position in the target order for all access requests to maintain the one or more of the two or more memory devices in the pre-determined position.
2. The system of claim 1 , wherein the logic is further to:
set the target order for the two or more memory devices to a random order based on the differentiator.
3. The system of claim 2 , wherein the logic is further to:
generate random numbers using the differentiator as a seed; and
set the target order for the two or more memory devices to the random order based on the generated random numbers.
4. The system of claim 3 , wherein the differentiator corresponds to one or more of a band number, an erase block number, or a stream identifier.
5. The system of claim 1 , wherein the logic is further to:
set the target order for the two or more memory devices based on an entry in a table corresponding to the differentiator.
6. The system of claim 1 , wherein the two or more memory devices comprise NAND die of a solid state drive.
7. A semiconductor apparatus, comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality logic hardware, the logic coupled to the one or more substrates to:
identify a differentiator associated with an access request for two or more memory devices,
set a target order for the two or more memory devices based on the differentiator, and
set a position in the target order for one or more of the two or more memory devices to a pre-determined position in the target order for all access requests to maintain the one or more of the two or more memory devices in the pre-determined position.
8. The apparatus of claim 7 , wherein the logic is further to:
set the target order for the two or more memory devices to a random order based on the differentiator.
9. The apparatus of claim 8 , wherein the logic is further to:
generate random numbers using the differentiator as a seed; and
set the target order for the two or more memory devices to the random order based on the generated random numbers.
10. The apparatus of claim 9 , wherein the differentiator corresponds to one or more of a band number, an erase block number, or a stream identifier.
11. The apparatus of claim 7 , wherein the logic is further to:
set the target order for the two or more memory devices based on an entry in a table corresponding to the differentiator.
12. The apparatus of claim 7 , wherein the two or more memory devices comprise NAND die of a solid state drive.
13. The apparatus of claim 7 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.
14. A method comprising:
identifying a differentiator associated with an access request for two or more memory devices;
setting a target order for the two or more memory devices based on the differentiator; and
setting a position in the target order for one or more of the two or more memory devices to a pre-determined position in the target order for all access requests to maintain the one or more of the two or more memory devices in the pre-determined position.
15. The method of claim 14 , further comprising:
setting the target order for the two or more memory devices to a random order based on the differentiator.
16. The method of claim 15 , further comprising:
generating random numbers using the differentiator as a seed; and
setting the target order for the two or more memory devices to the random order based on the generated random numbers.
17. The method of claim 16 , wherein the differentiator corresponds to one or more of a band number, an erase block number, or a stream identifier.
18. The method of claim 14 , further comprising:
setting the target order for the two or more memory devices based on an entry in a table corresponding to the differentiator.
19. The method of claim 14 , wherein the two or more memory devices comprise NAND die of a solid state drive.