Using variable voltages to discharge electrons from a memory array during verify recovery operations

1. An apparatus for preparing a non-volatile memory array comprised of wordlines and bitlines coupled to storage cells for application of pulses to the storage cells to program the storage cells, comprising:

a memory controller to:

in response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, concurrently to:

apply voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons that includes a staggered discharge that applies variable voltages to different groups of wordlines to cause different amounts of electrons to remain at storage cells coupled to the different groups of wordlines to avoid electrostatic high fields within the non-volatile memory array; and

apply voltages to the bitlines to perform bitline stabilization.

2. The apparatus of claim 1 , wherein when applying a variable voltage to a group of wordlines, the memory controller is further to apply a pass-through reset voltage to worldlines not in the group of wordlines to which the variable voltage is applied.

3. The apparatus of claim 1 , wherein the memory controller maintains an offset voltage for each group of wordlines, wherein different offset voltages are maintained for different of the groups of wordlines, wherein the memory controller is further to perform for each group of the groups of wordlines to discharge:

determine a variable voltage for the group of wordlines based on the offset voltage for the group of wordlines being discharged, wherein the determined variable voltage is applied to each of the wordlines in the group of wordlines to discharge electrons from the storage cells coupled to the wordlines in the group.

4. The apparatus of claim 3 , wherein to determine variable voltage for each of the group of wordlines based on the offset voltage comprises a prime voltage minus the offset voltage for the group of wordlines.

5. The apparatus of claim 4 , wherein the prime voltage comprises a program voltage minus a pass through voltage.

6. The apparatus of claim 1 , wherein to apply the voltages to the bitlines to perform bitline stabilization while applying voltages to the wordlines to discharge electrons comprises:

drive the bitlines to a supply voltage; and

in response to determining bitlines to inhibit and select while driving the bitlines to the supply voltage, drive the bitlines to inhibit to the supply voltage and drive the bitlines to select to ground.

7. The apparatus of claim 1 , wherein the memory controller is further to:

apply a pass through reset voltage to select gate drains and select gate sources coupled to strings of storage cells in the non-volatile memory array, through which the wordlines pass, concurrently while applying voltages to the bitlines and the wordlines.

8. The apparatus of claim 1 , wherein the non-volatile memory array comprises a three dimensional array of NAND storage cells.

9. A memory device, comprising:

a non-volatile memory array comprised of wordlines and bitlines coupled to storage cells for application of pulses to the storage cells to program the storage cells; and

a memory controller to:

in response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, concurrently to:

apply voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons that includes a staggered discharge that applies variable voltages to different groups of wordlines to cause different amounts of electrons to remain at storage cells coupled to the different groups of wordlines to avoid electrostatic high fields within the non-volatile memory array; and

apply voltages to the bitlines to perform bitline stabilization.

10. The memory device of claim 9 , wherein when applying a variable voltage to a group of wordlines, the memory controller is further to apply a pass-through reset voltage to worldlines not in the group of wordlines to which the variable voltage is applied.

11. The memory device of claim 9 , wherein the memory controller maintains an offset voltage for each group of wordlines, wherein different offset voltages are maintained for different of the groups of wordlines, wherein the memory controller is further to perform for each group of the groups of wordlines to discharge:

determine a variable voltage for the group of wordlines based on the offset voltage for the group of wordlines being discharged, wherein the determined variable voltage is applied to each of the wordlines in the group of wordlines to discharge electrons from the storage cells coupled to the wordlines in the group.

12. The memory device of claim 11 , wherein to determine variable voltage for each of the group of wordlines based on the offset voltage comprises a prime voltage minus the offset voltage for the group of wordlines.

13. The memory device of claim 12 , wherein the prime voltage comprises a program voltage minus a pass through voltage.

14. The memory device of claim 9 , wherein to apply the voltages to the bitlines to perform bitline stabilization while applying voltages to the wordlines to discharge electrons comprises:

drive the bitlines to a supply voltage; and

in response to determining bitlines to inhibit and select while driving the bitlines to the supply voltage, drive the bitlines to inhibit to the supply voltage and drive the bitlines to select to ground.

15. The memory device of claim 9 , wherein the memory controller is further to:

apply a pass through reset voltage to select gate drains and select gate sources coupled to strings of storage cells in the non-volatile memory array, through which the wordlines pass, concurrently while applying voltages to the bitlines and the wordlines.

16. A method for preparing a non-volatile memory array comprised of wordlines and bitlines coupled to storage cells for application of pulses to the storage cells to program the storage cells, comprising:

in response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, concurrently:

applying voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons that includes a staggered discharge that applies variable voltages to different groups of wordlines to cause different amounts of electrons to remain at storage cells coupled to the different groups of wordlines to avoid electrostatic high fields within the non-volatile memory array; and

applying voltages to the bitlines to perform bitline stabilization.

17. The method of claim 16 , wherein applying a variable voltage to a group of wordlines, further includes applying a pass-through reset voltage to worldlines not in the group of wordlines to which the variable voltage is applied.

18. The method of claim 16 , furthering comprising:

maintaining an offset voltage for each group of wordlines, wherein different offset voltages are maintained for different of the groups of wordlines, further performing for each group of the groups of wordlines to discharge; and

determining a variable voltage for the group of wordlines based on the offset voltage for the group of wordlines being discharged, wherein the determined variable voltage is applied to each of the wordlines in the group of wordlines to discharge electrons from the storage cells coupled to the wordlines in the group.

19. The method of claim 18 , wherein the determined variable voltage for each of the group of wordlines based on the offset voltage comprises a prime voltage minus the offset voltage for the group of wordlines.

20. The method of claim 19 , wherein the prime voltage comprises a program voltage minus a pass through voltage.

21. The method of claim 16 , wherein the applying the voltages to the bitlines to perform bitline stabilization while applying voltages to the wordlines to discharge electrons comprises:

driving the bitlines to a supply voltage; and

in response to determining bitlines to inhibit and select while driving the bitlines to the supply voltage, driving the bitlines to inhibit to the supply voltage and drive the bitlines to select to ground.

22. The method of claim 16 , further comprising:

applying a pass through reset voltage to select gate drains and select gate sources coupled to strings of storage cells in the non-volatile memory array, through which the wordlines pass, concurrently while applying voltages to the bitlines and the wordlines.