Channel conductivity in memory structures
A memory structure can include a conductive channel, a charge storage structure adjacent to the conductive channel, and a strain-inducing layer adjacent to the conductive channel on a side opposite the charge storage structure. The strain-inducing layer can have a higher coefficient of thermal expansion (CTE) than the conductive channel.
1. A memory structure, comprising:
a conductive channel;
a charge storage structure adjacent to the conductive channel; and
a strain-inducing layer adjacent to the conductive channel on a side opposite the charge storage structure, wherein the strain-inducing layer comprises at least one selected from a group consisting of silicon nitride, doped silicon nitride, doped silicon, silicon germanium, or a combination thereof;
wherein the strain-inducing layer comprises a dopant in an amount of from about 1 wt % to about 25 wt %;
wherein the strain-inducing layer is doped with oxygen in an amount of from about 5 wt % to about 20 wt %.
2. The memory structure of claim 1 , wherein the conductive channel comprises a doped polysilicon material.
3. The memory structure of claim 2 , wherein the conductive channel is P-type doped.
4. The memory structure of claim 2 , wherein the conductive channel is N-type doped.
5. The memory structure of claim 1 , wherein the charge storage structure comprises a floating gate memory structure.
6. The memory structure of claim 5 , wherein the floating gate memory structure comprises polysilicon.
7. The memory structure of claim 1 , wherein the charge storage structure comprises a charge trap memory structure.
8. The memory structure of claim 7 , wherein the charge trap memory structure comprises silicon nitride.
9. The memory structure of claim 1 , wherein the strain-inducing layer comprises Si x N (1-x) , where x is from about 0.3 to about 0.7.
10. The memory structure of claim 1 , wherein the strain-inducing layer is doped with carbon in an amount of from about 1 wt % to about 5 wt %.
11. The memory structure of claim 1 , wherein the strain-inducing layer has a higher coefficient of thermal expansion (CTE) than the conductive channel.
12. The memory structure of claim 11 , wherein the strain-inducing layer has a CTE of from about 0.5×10 −6 /° C. to about 4.0×10 −6 /° C.
13. The memory structure of claim 11 , wherein the difference in CTE between the conductive channel and the strain-inducing layer is at least about 0.5×10 −6 /° C.
14. The memory structure of claim 1 , wherein the strain-inducing layer has a higher lattice constant than the conductive channel.
15. The memory structure of claim 1 , wherein the strain-inducing layer has a thickness of from about 5 nm to about 20 nm.
16. The memory structure of claim 1 , further comprising an oxide layer between the conductive channel and the strain-inducing layer.
17. The memory structure of claim 16 , wherein the oxide layer has a thickness of from about 0.5 nm to about 1.5 nm.
18. The memory structure of claim 1 , further comprising an insulating material core, wherein the conductive channel is external to the insulating material core.
19. The memory structure of claim 18 , where the strain-inducing layer is positioned between the conductive channel and the insulating material core.
20. The memory structure of claim 18 , wherein the insulating material core comprises silicon oxide, silicon oxynitride, silicon oxycarbide, spin-on-glass, organic polymer, organic/inorganic co-polymer, or other combination thereof.
21. The memory structure of claim 18 , wherein the strain-inducing layer and the insulating material core comprise different dielectric materials.