Double data rate in parallel testing

1. An apparatus to test a semiconductor device, comprising:

a controller configured to perform one or more tests on the semiconductor device;

a reduce low pin count (RLPC) circuit configured to write data to the semiconductor device or read data from the semiconductor device at a double data rate (DDR) with respect to a single data rate (SDR); and

pad logic to couple to the semiconductor device, the pad logic configured to provide a trimmable data access time from clock (tAC) signal to select different access times of a single data rate (SDR) or a double data rate (DDR) mode of operation, wherein a loading time or an unloading time of the semiconductor device being tested, or a combination thereof, is reduced when a DDR mode is selected.

2. An apparatus as claimed in claim 1 , wherein the semiconductor device comprises NAND flash.

3. An apparatus as claimed in claim 1 , wherein the semiconductor device comprises double data rate (DDR) memory.

4. An apparatus as claimed in claim 1 , wherein one or more dummy clock cycles are added at a beginning or an end of a write and read cycle provided by the RLPC circuit to the semiconductor device to prime or flush a data pipe of data written to the semiconductor device.

5. An apparatus as claimed in claim 1 , wherein the RLPC circuit comprises:

a command mode selector;

a pin mode counter coupled to the command mode counter; and

control logic coupled to the command mode selector and the pin mode counter, the control logic to provide serial to parallel conversion of the write and read data.

6. A method to test a semiconductor device, comprising:

writing data to the semiconductor device and reading data from the semiconductor device at a double data rate (DDR) with respect to a single data rate (SDR) using a reduce low pin count (RLPC) circuit; and

providing a trimmable data access time from clock (tAC) signal to select different access times of the single data rate or the double data rate;

wherein a loading time or an unloading time of the semiconductor device being tested, or a combination thereof, is reduced when a DDR mode is selected.

7. A method as claimed in claim 6 , wherein the semiconductor device comprises NAND flash.

8. A method as claimed in claim 6 , wherein the semiconductor device comprises double data rate (DDR) memory.

9. A method as claimed in claim 6 , wherein one or more dummy clock cycles are added at a beginning or an end of a write and read cycle provided by the RLPC circuit to the semiconductor device to prime or flush a data pipe of data written to or read from the semiconductor device.

10. A method as claimed in claim 6 , further comprising:

adding one or more dummy cycles at a beginning of a serial input/output cycle, or at an end of a serial input/output cycle, or a combination thereof, to prime or flush a data pipe during a test.

11. An article of manufacture comprising a non-transitory storage medium having instructions stored thereon that, if executed, result in:

writing data to the semiconductor device and reading data from the semiconductor device at a double data rate (DDR) with respect to a single data rate (SDR) using a reduce low pin count (RLPC) circuit; and

providing a trimmable data access time from clock (tAC) signal to select different access times of the single data rate or the double data rate;

wherein a loading time or an unloading time of the semiconductor device being tested, or a combination thereof, is reduced when a DDR mode is selected.

12. An article of manufacture as claimed in claim 11 , wherein the semiconductor device comprises NAND flash.

13. An article of manufacture as claimed in claim 11 , wherein the semiconductor device comprises double data rate (DDR) memory.

14. An article of manufacture as claimed in claim 11 , wherein one or more dummy clock cycles are added at a beginning or an end of a write and read cycle provided by the RLPC circuit to the semiconductor device to prime or flush a data pipe of data written to or read from the semiconductor device.

15. An article of manufacture as claimed in claim 11 , further comprising:

adding one or more dummy cycles at a beginning of a serial input/output cycle, or at an end of a serial input/output cycle, or a combination thereof, to prime or flush a data pipe during a test.