Flash memory cells
3D NAND memory cells can include a source layer, a dielectric layer disposed on the source layer, and a select gate source (SGS) layer disposed on the dielectric layer. A plurality of alternating layers of conducting material and insulating material can be disposed on the SGS layer. A conductive channel can be formed within a cell pillar trench. The conductive channel can be in contact with the source layer and the plurality of alternating layers. The cell pillar trench can be positioned in a substantially perpendicular orientation with respect to the plurality of alternating layers.
1. A 3D NAND memory cell, comprising:
a source layer;
a dielectric layer disposed on the source layer;
a select gate source (SGS) layer disposed on the dielectric layer, wherein the thickness of the SGS layer is from about 2 times to about 5 times the thickness of the dielectric layer;
a plurality of alternating layers of conducting material and insulating material disposed on the SGS layer, said plurality of alternating layers having an SGS end proximate the SGS layer and a drain end distal to the SGS layer;
a tunnel dielectric layer formed within a cell pillar trench and extending along a sidewall of the cell pillar trench and laterally within the dielectric layer at least partially between the SGS layer and the source layer; and
a conductive channel formed within the cell pillar trench, said conductive channel connecting the source layer and the plurality of alternating layers, said cell pillar trench positioned in a substantially perpendicular orientation with respect to the plurality of alternating layers and having a diameter that differs by no more than 20% along a length thereof from the drain end to the SGS end of the plurality of alternating layers.
2. The memory cell of claim 1 , wherein the diameter differs by no more than 15%.
3. The memory cell of claim 1 , wherein the diameter differs by no more than 15 nanometers (nm).
4. The memory cell of claim 1 , wherein the diameter is from about 85 nm to about 115 nm.
5. The memory cell of claim 1 , wherein the diameter of the cell pillar trench at the SGS end is from about 1.25 times to about 3.5 times the thickness of the dielectric layer.
6. The memory cell of claim 1 , wherein the thickness of the dielectric layer is from about 30 nm to about 70 nm.
7. The memory cell of claim 1 , wherein the dielectric layer is an oxide layer.
8. The memory cell of claim 1 , wherein the conductive channel comprises a doped polysilicon material.
9. The memory cell of claim 8 , wherein the conductive channel is P-type doped.
10. The memory cell of claim 8 , wherein the conductive channel is N-type doped.
11. A flash memory structure, comprising:
a source layer;
a dielectric layer disposed on the source layer;
a select gate source (SGS) layer disposed on the dielectric layer, wherein the thickness of the SGS layer is from about 2 times to about 5 times the thickness of the dielectric layer;
a plurality of alternating layers of conducting material and insulating material disposed on the SGS layer, said plurality of alternating layers having an SGS end proximate the SGS layer and a drain end distal to the SGS layer;
a tunnel dielectric layer formed within a cell pillar trench and extending along a sidewall of the cell pillar trench and laterally within the dielectric layer at least partially between the SGS layer and the source layer;
a conductive channel formed within the cell pillar trench, said conductive channel connecting the source layer and the plurality of alternating layers, said cell pillar trench positioned in a substantially perpendicular orientation with respect to the plurality of alternating layers and having a diameter that differs by no more than 20% along a length thereof from the drain end to the SGS end of the plurality of alternating layers; and
an array of memory structures arranged in a three-dimensional configuration around the conductive channel, wherein the memory structures are aligned with and electrically coupled to the conductive material layers.
12. The flash memory structure of claim 11 , wherein the diameter differs by no more than 15%.
13. The flash memory structure of claim 11 , wherein the diameter differs by no more than 15 nanometers (nm).
14. The flash memory structure of claim 11 , wherein the diameter is from about 85 nm to about 115 nm.
15. The flash memory structure of claim 11 , wherein the diameter of the cell pillar at the SGS end is from about 1.25 times to about 3.5 times the thickness of the dielectric layer.
16. The flash memory structure of claim 11 , wherein the thickness of the dielectric layer is from about 30 nm to about 70 nm.
17. The flash memory structure of claim 11 , wherein the conductive channel comprises a doped polysilicon material.
18. The flash memory structure of claim 11 , further comprising a tunnel dielectric layer between the conductive channel and the array of memory structures.