Multi-level memory cell sensing
View Patent ↗The delay arising from wordline capacitance in multi-level memories may be reduced by adding switched transistors along the wordline path. Also, the wordline may be pre-charged to a high level and then the first wordline voltage level for reading may be a center level. The switched transistors may be p-devices whose n-wells are biased by a stable DC voltage. Nodes along the wordline may float when not accessed. Finally, a distributed voltage generator may be used.
1. A method comprising:
generating at least three selectable wordline voltages for a wordline path of multi-level memory;
supplying said voltages through at least two switched transistors along the wordline path; and
sensing an intermediate wordline voltage level of said at least three selectable wordline voltages, then sensing the lower of said three selectable wordline voltages and then sensing the higher of said three wordline voltages.
2. The method of claim 1 including forming said switched transistors of p-type transistors.
3. The method of claim 2 including providing a stable DC bias potential to the n-wells of said p-type transistors.
4. The method of claim 3 including providing a stable DC bias potential that is always asserted in selected in deselected memory planes.
5. The method of claim 1 including allowing the wordline path to float when the wordline path is not accessed.
6. The method of claim 1 including providing one generator to generate said three selectable wordline voltages for each of a plurality of partitions.
7. The method of claim 1 including pre-charging said wordline path to the higher of said three voltages.
8. The method of claim 1 including generating voltages for a multi-level flash memory.
9. The method of claim 1 including generating voltages for a multi-level flash memory having four different levels.
10. A multi-level memory comprising:
a plurality of multi-level memory cells along a wordline;
a wordline decoder to generate at least three selectable wordline voltages for said wordline, said decoder including a wordline voltage generator to first sense an intermediate wordline voltage level of said at least three selectable wordline voltages, then sense the lower of said three selectable wordline voltages, and then sense the higher of said three wordline voltages; and
at least two switched transistors along said wordline.
11. The memory of claim 10 wherein said memory is a flash memory.
12. The memory of claim 10 wherein said transistors are p-type transistors.
13. The memory of claim 12 wherein said p-type transistors are supplied with a stable DC bias voltage on their n-wells.
14. The memory of claim 13 wherein said stable DC bias voltage is asserted in selected and deselected memory planes.
15. The memory of claim 10 wherein said wordline path floats when the wordline is not accessed.
16. The memory of claim 10 including at least one partition and a generator to generate three selectable wordline voltages for each partition.
17. The memory of claim 10 wherein said wordline decoder to pre-charge the wordline to the higher of said three selectable voltages.
18. The memory of claim 10 wherein said memory is a multi-level flash memory having four memory levels.
19. A system comprising:
a processor;
a wireless interface coupled to said processor; and
a multi-level memory coupled to said processor including a plurality of multi-level memory cells along a wordline, a wordline decoder to generate at least three selectable wordline voltages for said wordline, and at least two switched transistors along said wordline, wherein said wordline path floats when the wordline is not accessed.
20. The system of claim 19 wherein said memory is a flash memory.
21. The system of claim 19 wherein said memory is a multi-level flash memory having four memory levels.
22. The system of claim 19 wherein said transistors are p-type transistors.
23. The system of claim 22 wherein said p-type transistors are supplied with a stable DC bias voltage on their n-wells.