Parity checking circuit for continuous checking of the parity of a memory cell
A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload data word to be stored, with the parity checking circuit being formed from four transistors of the same conductance type. The parity checking circuit has a detector, which automatically detects the change in an information state of a memory cell. The detector is in the form of an automatic state device and has a number of catch latches.
1. A parity checking system for continuous parity checking of memory cells of a memory cell array configured to store an original payload data word of M bits, comprising:
a plurality of parity checking circuits, where each parity checking circuit is connected to a corresponding memory cell of the memory cell array and configured to continuously check a parity of the corresponding memory cell, each parity checking circuit comprising:
a first parity input and a second parity input;
a first parity output and a second parity output;
a first transistor connected between the first parity input and the second parity input;
a second transistor connected between the second parity input and the first parity output;
a third transistor connected between the second parity input and the second parity output;
a fourth transistor connected between the first parity input and the first parity output;
where each of the first, second, third, and fourth transistors comprise a gate connected to a memory cell of the memory cell array; and
where each of the first, second, third, and fourth transistors comprise the same conductance type; and
where the number N of parity checking circuits in the plurality of parity checking circuits equals the number M of bits in the original payload data word.
2. The parity checking system of claim 1 , where each of the first, second, third, and fourth transistors comprise the same conductance type.
3. The parity checking system of claim 1 , where the gates of the first and second transistors are connected to a first memory node of the memory cell and the gates of the third and fourth transistors are connected to a second memory node of the memory cell.
4. The parity checking system of claim 1 , further comprising a precharge circuit connected to the first and second parity outputs.
5. The parity checking system of claim 4 , where the precharge circuit comprises:
a precharge line input;
a first precharge transistor comprising:
a source connected to the first parity output; and
a drain connected to a voltage source potential;
a second precharge transistor comprising:
a source connected to the voltage source potential; and
a drain connected to the second parity output; and
where first and second precharge transistors each comprise a gate connected to the precharge line input.
6. The parity checking circuit of claim 5 , where each of the first, second, third, and fourth transistors comprise a first conductance type, and each of the first and second precharge transistors comprise a second conductance type opposite to the first conductance type.
7. The parity checking system of claim 6 , where the precharge line input comprises a complementary control line input.
8. The parity checking system of claim 5 , where the first and second parity outputs each comprise an electrical connection to a detector that detects a change in an information state of the memory cell.
9. The parity checking system of claim 8 , where the detector comprises an automatic state device that comprises:
a first state class that characterizes an initialization state;
a second state class that characterizes normal operation; and
a third state class that characterizes a fault.
10. The parity checking system of claim 9 , where a state class change is irreversible.
11. The parity checking system of claim 8 , where the detector comprises a first catch latch and a second catch latch.
12. The parity checking system of claim 11 , where each of the first and second catch latches comprise:
a latch input;
a latch output;
a first inverter comprising a first inverter input and a first inverter output;
a first circuit node connected to the first inverter input;
a second circuit node connected to the inverter output and to the latch output;
a first latch transistor comprising:
a gate connected to the latch input;
a drain connected to the first circuit node; and
a source connected to a ground potential;
a second latch transistor comprising:
a gate connected to the second circuit node;
a drain connected to the ground potential; and
a source connected to the first circuit node; and
where the first and second latch transistors each comprise a first conductance type.
13. The parity checking system of claim 12 , where each catch latch further comprises:
a complementary control line input;
a third latch transistor comprising:
a gate connected to the complementary control line input;
a drain connected to the first circuit node; and
a source connected to a supply voltage potential;
a fourth latch transistor comprising:
a gate connected to the second circuit node;
a drain connected to the supply voltage potential; and
a source connected to the first circuit node; and
where the third and fourth transistors each comprise a second conductance type opposite to the first conductance type.
14. The parity checking system of claim 12 , where each catch latch further comprises:
a control line input;
a second inverter comprising:
a second inverter input connected to the second circuit node; and
a second inverter output;
a third latch transistor comprising:
a gate connected to the control line input;
a drain connected to a supply voltage potential; and
a source connected to the first circuit node;
a fourth latch transistor comprising:
a gate connected to the second inverter output;
a drain connected to the first circuit node; and
a source connected to the supply voltage potential; and
where the third and fourth transistors each comprise a second conductance type that is the same as the first conductance type.
15. The parity checking system of claim 8 , where the detector comprises a first output providing a first output signal and a second output providing a second output signal, and where the first and second outputs are connected to inputs of a logic circuit configured to reduce the first and second output signals to a 1-bit signal.
16. The parity checking system of claim 15 , where the logic circuit comprises an AND gate.
17. The parity checking system of claim 1 , where the first, second, third, and fourth transistors are cross-coupled.
18. The parity checking system of claim 1 , where a source connection of the first transistor is connected to a source connection of the fourth transistor, a source connection of the second transistor is connected to a source connection of the third transistor, and a drain connection of the second transistor is connected to a drain connection of the fourth transistor, and a drain connection of the first transistor is connected to a drain connection of the third transistor.
19. The parity checking system of claim 1 , where:
the first transistor comprises:
a source connected to the first parity input; and
a drain connected to the second parity output; and
the second transistor comprises:
a source connected to the second parity input; and
a drain connected to the first parity output.
20. The parity checking system of claim 1 , where:
the third transistor comprises:
a source connected to the second parity input; and
a drain connected to the second parity output; and
the fourth transistor comprises:
a source connected to the first parity input; and
a drain connected to the first parity output.