Efficent column redundancy techniques
View Patent ↗The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a multi-bank memory. The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit adapted to complete a word for a failing bank in the multi-bank memory.
1. A method for operating a memory device comprising:
selecting a multiplexer;
accessing failing bits in a multi-bank memory in the memory device using said multiplexer;
accessing a sense amplifier when said multiplexer is selected;
generating at least one multiplexer signal; and
activating at least one transmission gate using said at least one multiplexer signal.
2. The method of claim 1 comprising routing signals to said multiplexer using a routing channel.
3. The method of claim 2 comprising interfacing said routing channel with at least said sense amplifier.
4. The method of claim 1 comprising passing signals to said sense amplifier using said at least one transmission gate.
5. A method for operating a memory device comprising:
selecting a multiplexer;
accessing failing bits in a multi-bank memory in the memory device using said multiplexer;
accessing a sense amplifier when said multiplexer is selected;
generating at least one multiplexer signal; and
activating at least one transmission gate using said at least one multiplexer signal.
6. The method of claim 5 comprising routing signals to said multiplexer using a routing channel.
7. The method of claim 6 comprising interfacing said routing channel with at least said sense amplifier.
8. The method of claim 5 comprising passing signals to said sense amplifier using said at least one transmission gate.
9. A method for operating a memory architecture, the method comprising:
accessing failing bits in a multi-bank memory in a self-timed local element of the memory architecture using at least one multiplexer;
interfacing with a synchronous controlled global element of the memory architecture using said at least one multiplexer;
accessing a sense amplifier when said at least one multiplexer is selected;
generating at least one multiplexer signal; and
activating at least one transmission gate using said at least one multiplexer signal, wherein said multi-bank memory comprises at least one redundant bank having at least one output data bit adapted to complete a word for a failing bank in said multi-bank memory.
10. The method of claim 9 comprising selecting said at least one multiplexer.
11. The method of claim 10 comprising shifting out at least one of said failing bits using a shifter block when said at least one multiplexer is selected, said shifter block having at least one input data bit and at least one output data bit.
12. The method of claim 11 wherein said multiplexer is a failing multiplexer.
13. The method of claim 12 comprising passing said at least one input data bit directly to said at least one output data bit using said shifter block when said failing multiplexer is not selected.
14. The method of claim 9 comprising accessing said sense amplifier.
15. The method of claim 9 comprising routing signals to said at least one multiplexer using a routing channel interfacing with at least said sense amplifier.
16. The method of claim 9 , comprising passing signals to said at least one sense amplifier using said at least one transmission gate.
17. The method of claim 9 comprising routing m multiplexer signals using a channel router.
18. A method for operating a memory architecture having a global element and a self-timed local element, the self-timed local element having at least one multi-bank memory, the method comprising:
accessing failing bits in a multi-bank memory in the self-timed local element using at least one multiplexer, said multi-bank memory comprising at least one redundant bank having at least one output data bit adapted to complete a word for a failing bank in said multi-bank memory;
interfacing with a synchronous controlled global element using said at least one multiplexer;
accessing a sense amplifier when said at least one multiplexer is selected; and
activating at least one transmission gate using multiplexer signals.
19. The method of claim 18 comprising selecting at least one multiplexer.
20. The method of claim 19 comprising accessing said sense amplifier.
21. The method of claim 20 comprising routing m multiplexer signals using a channel router.
22. The method of claim 19 comprising routing signals to said at least one multiplexer using a routing channel interfacing with at least said sense amplifier in said local element.
23. The method of claim 22 , comprising passing signals to said at least one sense amplifier using said at least one transmission gate.
24. The method of claim 19 comprising shifting out at least one of said failing bits using a shifter block when said at least one multiplexer is selected, said shifter block having at least one input data bit and at least one output data bit.
25. The method of claim 24 wherein said multiplexer is a failing multiplexer.
26. The method of claim 25 comprising passing said at least one input data bit directly to said at least one output data bit using said shifter block when said failing multiplexer is not selected.