NANO-electronic memory array
View Patent ↗Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assemblying one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.
1. A memory device, comprising: an array of memory cells disposed in rows and columns and constructed over a substrate, each memory cell comprising a first signal electrode, a second signal electrode, and a single molecule magnetic nano-layer disposed in the intersecting region between the first signal electrode and the second signal electrode, a plurality of word lines each connecting the first signal electrodes of a row of memory cells; and a plurality of bit lines each connecting the second signal electrodes of a column of memory cells.
2. The memory device of claim 1 , further comprising a driver circuit for selectively controlling the first signal electrodes or the second signal electrodes.
3. The memory device of claim 2 , wherein the circuit includes one or more of a Y gate, a sense amplifier, an input-output buffer, an X address decoder, a Y address decoder, and an address buffer.
4. The memory device of claim 1 , wherein the substrate includes a silicon-on-insulator wafer.
5. The memory device of claim 1 , wherein the NANO-magnetic layer is spin-coated over the substrate wherein first signal electrodes and the second signal electrodes are constructed.
6. The memory device of claim 1 , wherein the single molecule magnets can form crystals that optionally are characterized by a monodisperse distribution.
7. The memory device of claim 1 , wherein the single molecule magnets include a core of strongly exchange-coupled transition metal ions in the molecule.
8. The memory device of claim 1 , further comprising an array of redundant NANO elements.
9. The memory device of claim 8 , wherein the redundant array is a row or a column of redundant NANO-elements.
10. The memory device of claim 1 , wherein the NANO-layer comprises optical NANO-elements.
11. The memory device of claim 1 , further comprising memory devices forming a plurality of memory hierarchy to optimize data access speed.
12. The device of claim 1 , further comprising one or more programmable analog cells having one or more NANO-elements.
13. The device of claim 1 , further comprising a programmable logic nano-element coupled between a first node of the programmable analog cell and an input of the active circuit or between the input of the active circuit and an output of the active circuit.
14. A memory electronic device, comprising: a substrate; a first conductive layer fabricated using semiconductor fabrication techniques; a second conductive layer formed above the first conductive layer, the second conductive layer having one or more NANO-molecular bonding areas; one or mor& single molecule magnetic NANO memory elements self-assembled to the second conductive layer NANO-molecular bonding areas.
15. The device of claim 14 , wherein the NANO-elements is disposed in an array pattern.
16. The device of claim 14 , wherein the NANO-elements are spin-coated on the second layer.